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[MIPS] IP28: added cache barrier to assembly routines

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IP28 needs special treatment to avoid speculative accesses. gcc
takes care for .c code, but for assembly code we need to do it
manually.

This is taken from Peter Fuersts IP28 patches.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer
2007-11-25 11:47:56 +01:00
committed by Ralf Baechle
parent 2064ba23e5
commit 930bff8822
4 changed files with 24 additions and 0 deletions
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arch/mips/lib/strncpy_user.S
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@@ -38,6 +38,7 @@ FEXPORT(__strncpy_from_user_nocheck_asm)
.set noreorder
1: EX(lbu, t0, (v1), fault)
PTR_ADDIU v1, 1
R10KCBARRIER(0(ra))
beqz t0, 2f
sb t0, (a0)
PTR_ADDIU v0, 1