ath5k: Reset cleanup and generic cleanup
* No functional changes * Clean up reset: Introduce init functions for each unit and call them instead of having everything inside ath5k_hw_reset (it's just c/p for now so nothing changes except calling order -I tested it with various cards and it's ok-) * Further cleanups: ofdm_timings belongs to phy.c rate_duration belongs to pcu.c clock functions are general and belong to reset.c (more to follow) * Reorder functions for better organization: We start with helpers and other functions follow in categories, init functions are last Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis
committed by
John W. Linville
John W. Linville
parent
ea066d5a91
commit
9320b5c4a7
@ -29,6 +29,95 @@
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#include "rfbuffer.h"
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#include "rfgain.h"
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/******************\
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* Helper functions *
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\******************/
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/*
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* Get the PHY Chip revision
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*/
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u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
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{
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unsigned int i;
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u32 srev;
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u16 ret;
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/*
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* Set the radio chip access register
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*/
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switch (chan) {
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case CHANNEL_2GHZ:
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
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break;
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case CHANNEL_5GHZ:
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
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break;
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default:
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return 0;
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}
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mdelay(2);
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/* ...wait until PHY is ready and read the selected radio revision */
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ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
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for (i = 0; i < 8; i++)
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ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
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if (ah->ah_version == AR5K_AR5210) {
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srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
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ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
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} else {
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srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
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ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
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((srev & 0x0f) << 4), 8);
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}
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/* Reset to the 5GHz mode */
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
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return ret;
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}
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/*
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* Check if a channel is supported
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*/
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bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
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{
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/* Check if the channel is in our supported range */
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if (flags & CHANNEL_2GHZ) {
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if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
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(freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
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return true;
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} else if (flags & CHANNEL_5GHZ)
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if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
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(freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
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return true;
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return false;
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}
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bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
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struct ieee80211_channel *channel)
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{
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u8 refclk_freq;
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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refclk_freq = 40;
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else
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refclk_freq = 32;
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if ((channel->center_freq % refclk_freq != 0) &&
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((channel->center_freq % refclk_freq < 10) ||
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(channel->center_freq % refclk_freq > 22)))
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return true;
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else
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return false;
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}
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/*
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* Used to modify RF Banks before writing them to AR5K_RF_BUFFER
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*/
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@ -110,6 +199,78 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
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return data;
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}
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/**
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* ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
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*
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* @ah: the &struct ath5k_hw
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* @channel: the currently set channel upon reset
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*
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* Write the delta slope coefficient (used on pilot tracking ?) for OFDM
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* operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
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*
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* Since delta slope is floating point we split it on its exponent and
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* mantissa and provide these values on hw.
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*
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* For more infos i think this patent is related
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* http://www.freepatentsonline.com/7184495.html
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*/
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static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
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struct ieee80211_channel *channel)
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{
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/* Get exponent and mantissa and set it */
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u32 coef_scaled, coef_exp, coef_man,
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ds_coef_exp, ds_coef_man, clock;
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BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
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!(channel->hw_value & CHANNEL_OFDM));
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/* Get coefficient
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* ALGO: coef = (5 * clock / carrier_freq) / 2
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* we scale coef by shifting clock value by 24 for
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* better precision since we use integers */
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/* TODO: Half/quarter rate */
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clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
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coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
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/* Get exponent
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* ALGO: coef_exp = 14 - highest set bit position */
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coef_exp = ilog2(coef_scaled);
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/* Doesn't make sense if it's zero*/
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if (!coef_scaled || !coef_exp)
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return -EINVAL;
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/* Note: we've shifted coef_scaled by 24 */
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coef_exp = 14 - (coef_exp - 24);
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/* Get mantissa (significant digits)
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* ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
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coef_man = coef_scaled +
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(1 << (24 - coef_exp - 1));
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/* Calculate delta slope coefficient exponent
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* and mantissa (remove scaling) and set them on hw */
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ds_coef_man = coef_man >> (24 - coef_exp);
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ds_coef_exp = coef_exp - 16;
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
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AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
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AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
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return 0;
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}
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int ath5k_hw_phy_disable(struct ath5k_hw *ah)
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{
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/*Just a try M.F.*/
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ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
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return 0;
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}
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/**********************\
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* RF Gain optimization *
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\**********************/
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@ -436,7 +597,7 @@ done:
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/* Write initial RF gain table to set the RF sensitivity
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* this one works on all RF chips and has nothing to do
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* with gain_F calibration */
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int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
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static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
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{
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const struct ath5k_ini_rfgain *ath5k_rfg;
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unsigned int i, size;
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@ -494,12 +655,11 @@ int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
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* RF Registers setup *
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\********************/
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/*
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* Setup RF registers by writing RF buffer on hw
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*/
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int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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unsigned int mode)
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static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
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struct ieee80211_channel *channel, unsigned int mode)
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{
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const struct ath5k_rf_reg *rf_regs;
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const struct ath5k_ini_rfbuffer *ini_rfb;
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@ -821,24 +981,6 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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PHY/RF channel functions
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\**************************/
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/*
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* Check if a channel is supported
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*/
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bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
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{
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/* Check if the channel is in our supported range */
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if (flags & CHANNEL_2GHZ) {
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if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
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(freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
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return true;
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} else if (flags & CHANNEL_5GHZ)
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if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
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(freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
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return true;
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return false;
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}
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/*
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* Convertion needed for RF5110
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*/
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@ -1045,7 +1187,8 @@ static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
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/*
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* Set a channel on the radio chip
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*/
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int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
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static int ath5k_hw_channel(struct ath5k_hw *ah,
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struct ieee80211_channel *channel)
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{
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int ret;
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/*
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@ -1419,31 +1562,12 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
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return ret;
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}
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/***************************\
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* Spur mitigation functions *
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\***************************/
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bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
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struct ieee80211_channel *channel)
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{
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u8 refclk_freq;
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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refclk_freq = 40;
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else
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refclk_freq = 32;
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if ((channel->center_freq % refclk_freq != 0) &&
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((channel->center_freq % refclk_freq < 10) ||
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(channel->center_freq % refclk_freq > 22)))
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return true;
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else
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return false;
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}
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void
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static void
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ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
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struct ieee80211_channel *channel)
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{
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@ -1666,63 +1790,6 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
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}
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}
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/********************\
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Misc PHY functions
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\********************/
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int ath5k_hw_phy_disable(struct ath5k_hw *ah)
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{
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/*Just a try M.F.*/
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ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
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return 0;
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}
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/*
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* Get the PHY Chip revision
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*/
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u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
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{
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unsigned int i;
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u32 srev;
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u16 ret;
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/*
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* Set the radio chip access register
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*/
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switch (chan) {
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case CHANNEL_2GHZ:
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
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break;
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case CHANNEL_5GHZ:
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
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break;
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default:
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return 0;
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}
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mdelay(2);
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/* ...wait until PHY is ready and read the selected radio revision */
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ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
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for (i = 0; i < 8; i++)
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ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
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if (ah->ah_version == AR5K_AR5210) {
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srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
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ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
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} else {
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srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
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ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
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((srev & 0x0f) << 4), 8);
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}
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/* Reset to the 5GHz mode */
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
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return ret;
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}
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/*****************\
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* Antenna control *
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@ -2984,7 +3051,7 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
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/*
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* Set transmission power
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*/
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int
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static int
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ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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u8 ee_mode, u8 txpower)
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{
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@ -3108,3 +3175,176 @@ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
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return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
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}
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/*************\
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Init function
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\*************/
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int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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u8 mode, u8 ee_mode, u8 freq)
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{
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int ret, i;
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u32 phy_tst1;
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ret = 0;
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/*
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* 5211/5212 Specific
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*/
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if (ah->ah_version != AR5K_AR5210) {
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/*
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* Write initial RF gain settings
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* This should work for both 5111/5112
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*/
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ret = ath5k_hw_rfgain_init(ah, freq);
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if (ret)
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return ret;
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mdelay(1);
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/*
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* Set TX power
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*/
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ret = ath5k_hw_txpower(ah, channel, ee_mode,
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ah->ah_txpower.txp_max_pwr / 2);
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if (ret)
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return ret;
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/*
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* Write RF buffer
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*/
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ret = ath5k_hw_rfregs_init(ah, channel, mode);
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if (ret)
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return ret;
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/* Write OFDM timings on 5212*/
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if (ah->ah_version == AR5K_AR5212 &&
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channel->hw_value & CHANNEL_OFDM) {
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ret = ath5k_hw_write_ofdm_timings(ah, channel);
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if (ret)
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return ret;
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/* Spur info is available only from EEPROM versions
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* greater than 5.3, but the EEPROM routines will use
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* static values for older versions */
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if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
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ath5k_hw_set_spur_mitigation_filter(ah,
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channel);
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}
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/*Enable/disable 802.11b mode on 5111
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(enable 2111 frequency converter + CCK)*/
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if (ah->ah_radio == AR5K_RF5111) {
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if (mode == AR5K_MODE_11B)
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AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
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AR5K_TXCFG_B_MODE);
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else
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AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
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AR5K_TXCFG_B_MODE);
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}
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} else {
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/*
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* For 5210 we do all initialization using
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* initvals, so we don't have to modify
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* any settings (5210 also only supports
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* a/aturbo modes)
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*/
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mdelay(1);
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/* Disable phy and wait */
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ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
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mdelay(1);
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}
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/* Set channel on PHY */
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ret = ath5k_hw_channel(ah, channel);
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if (ret)
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return ret;
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/*
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* Enable the PHY and wait until completion
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* This includes BaseBand and Synthesizer
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* activation.
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*/
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ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
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/*
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* On 5211+ read activation -> rx delay
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* and use it.
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*
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* TODO: Half/quarter rate support
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*/
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if (ah->ah_version != AR5K_AR5210) {
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u32 delay;
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delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
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AR5K_PHY_RX_DELAY_M;
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delay = (channel->hw_value & CHANNEL_CCK) ?
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((delay << 2) / 22) : (delay / 10);
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udelay(100 + (2 * delay));
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} else {
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Perform ADC test to see if baseband is ready
|
||||
* Set TX hold and check ADC test register
|
||||
*/
|
||||
phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
|
||||
ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
|
||||
for (i = 0; i <= 20; i++) {
|
||||
if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
|
||||
break;
|
||||
udelay(200);
|
||||
}
|
||||
ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
|
||||
|
||||
/*
|
||||
* Start automatic gain control calibration
|
||||
*
|
||||
* During AGC calibration RX path is re-routed to
|
||||
* a power detector so we don't receive anything.
|
||||
*
|
||||
* This method is used to calibrate some static offsets
|
||||
* used together with on-the fly I/Q calibration (the
|
||||
* one performed via ath5k_hw_phy_calibrate), which doesn't
|
||||
* interrupt rx path.
|
||||
*
|
||||
* While rx path is re-routed to the power detector we also
|
||||
* start a noise floor calibration to measure the
|
||||
* card's noise floor (the noise we measure when we are not
|
||||
* transmitting or receiving anything).
|
||||
*
|
||||
* If we are in a noisy environment, AGC calibration may time
|
||||
* out and/or noise floor calibration might timeout.
|
||||
*/
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
|
||||
AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
|
||||
|
||||
/* At the same time start I/Q calibration for QAM constellation
|
||||
* -no need for CCK- */
|
||||
ah->ah_calibration = false;
|
||||
if (!(mode == AR5K_MODE_11B)) {
|
||||
ah->ah_calibration = true;
|
||||
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
|
||||
AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
|
||||
AR5K_PHY_IQ_RUN);
|
||||
}
|
||||
|
||||
/* Wait for gain calibration to finish (we check for I/Q calibration
|
||||
* during ath5k_phy_calibrate) */
|
||||
if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
|
||||
AR5K_PHY_AGCCTL_CAL, 0, false)) {
|
||||
ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
|
||||
channel->center_freq);
|
||||
}
|
||||
|
||||
/* Restore antenna mode */
|
||||
ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user