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[ARM] 5336/1: Formatting/Whitespace cleanups in mach-sa1100

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This patch fixes bad formatting found in
mach-sa1100 files.

What it does is to replace/delete things like
excessive spaces (start || endline). The code
looks the same just alot less junk.

Signed-off-by: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Kristoffer Ericson
2008-11-26 20:58:43 +01:00
committed by Russell King
parent 799a0600ac
commit 93982535a2
10 changed files with 87 additions and 88 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
arch/arm/mach-sa1100/collie.c
View File

@@ -68,23 +68,22 @@ struct platform_device colliescoop_device = {
};
static struct scoop_pcmcia_dev collie_pcmcia_scoop[] = {
{
.dev = &colliescoop_device.dev,
.irq = COLLIE_IRQ_GPIO_CF_IRQ,
.cd_irq = COLLIE_IRQ_GPIO_CF_CD,
.cd_irq_str = "PCMCIA0 CD",
},
{
.dev = &colliescoop_device.dev,
.irq = COLLIE_IRQ_GPIO_CF_IRQ,
.cd_irq = COLLIE_IRQ_GPIO_CF_CD,
.cd_irq_str = "PCMCIA0 CD",
},
};
static struct scoop_pcmcia_config collie_pcmcia_config = {
.devs = &collie_pcmcia_scoop[0],
.num_devs = 1,
.devs = &collie_pcmcia_scoop[0],
.num_devs = 1,
};
static struct mcp_plat_data collie_mcp_data = {
.mccr0 = MCCR0_ADM | MCCR0_ExtClk,
.sclk_rate = 9216000,
.mccr0 = MCCR0_ADM | MCCR0_ExtClk,
.sclk_rate = 9216000,
};
#ifdef CONFIG_SHARP_LOCOMO
@@ -95,14 +94,14 @@ struct platform_device collie_locomo_device;
static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl)
{
if (mctrl & TIOCM_RTS)
if (mctrl & TIOCM_RTS)
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0);
else
else
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1);
if (mctrl & TIOCM_DTR)
if (mctrl & TIOCM_DTR)
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0);
else
else
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1);
}

20
arch/arm/mach-sa1100/collie_pm.c
View File

@@ -263,24 +263,24 @@ static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev)
}
static struct ucb1x00_driver collie_pm_ucb_driver = {
.add = collie_pm_ucb_add,
.add = collie_pm_ucb_add,
};
static struct platform_device *collie_pm_device;
static int __init collie_pm_init(void)
{
int ret;
int ret;
collie_pm_device = platform_device_alloc("sharpsl-pm", -1);
if (!collie_pm_device)
return -ENOMEM;
collie_pm_device = platform_device_alloc("sharpsl-pm", -1);
if (!collie_pm_device)
return -ENOMEM;
collie_pm_device->dev.platform_data = &collie_pm_machinfo;
ret = platform_device_add(collie_pm_device);
collie_pm_device->dev.platform_data = &collie_pm_machinfo;
ret = platform_device_add(collie_pm_device);
if (ret)
platform_device_put(collie_pm_device);
if (ret)
platform_device_put(collie_pm_device);
if (!ret)
ret = ucb1x00_register_driver(&collie_pm_ucb_driver);
@@ -291,7 +291,7 @@ static int __init collie_pm_init(void)
static void __exit collie_pm_exit(void)
{
ucb1x00_unregister_driver(&collie_pm_ucb_driver);
platform_device_unregister(collie_pm_device);
platform_device_unregister(collie_pm_device);
}
module_init(collie_pm_init);

16
arch/arm/mach-sa1100/cpu-sa1110.c
View File

@@ -81,14 +81,14 @@ static struct sdram_params sdram_tbl[] __initdata = {
.twr = 9,
.refresh = 64000,
.cas_latency = 3,
}, { /* Samsung K4S281632B-1H */
.name = "K4S281632B-1H",
.rows = 12,
.tck = 10,
.trp = 20,
.twr = 10,
.refresh = 64000,
.cas_latency = 3,
}, { /* Samsung K4S281632B-1H */
.name = "K4S281632B-1H",
.rows = 12,
.tck = 10,
.trp = 20,
.twr = 10,
.refresh = 64000,
.cas_latency = 3,
}, { /* Samsung KM416S4030CT */
.name = "KM416S4030CT",
.rows = 13,

8
arch/arm/mach-sa1100/dma.c
View File

@@ -113,10 +113,10 @@ int sa1100_request_dma (dma_device_t device, const char *device_id,
}
}
if (!err) {
if (dma)
dma->device = device;
else
err = -ENOSR;
if (dma)
dma->device = device;
else
err = -ENOSR;
}
spin_unlock(&dma_list_lock);
if (err)

12
arch/arm/mach-sa1100/include/mach/h3600.h
View File

@@ -32,14 +32,14 @@ typedef int __bitwise pm_request_t;
#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800())
/* Physical memory regions corresponding to chip selects */
#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000)
#define H3600_BANK_2_PHYS SA1100_CS2_PHYS
#define H3600_BANK_4_PHYS SA1100_CS4_PHYS
#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000)
#define H3600_BANK_2_PHYS SA1100_CS2_PHYS
#define H3600_BANK_4_PHYS SA1100_CS4_PHYS
/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
#define H3600_EGPIO_VIRT 0xf0000000
#define H3600_BANK_2_VIRT 0xf1000000
#define H3600_BANK_4_VIRT 0xf3800000
#define H3600_EGPIO_VIRT 0xf0000000
#define H3600_BANK_2_VIRT 0xf1000000
#define H3600_BANK_4_VIRT 0xf3800000
/*
Machine-independent GPIO definitions

10
arch/arm/mach-sa1100/pleb.c
View File

@@ -122,12 +122,12 @@ static void __init pleb_map_io(void)
sa1100_map_io();
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
sa1100_register_uart(1, 1);
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/*
* Fix expansion memory timing for network card

52
arch/arm/mach-sa1100/sleep.S
View File

@@ -100,36 +100,36 @@ ENTRY(sa1100_cpu_suspend)
ldr r1, =MSC1
ldr r2, =MSC2
ldr r3, [r0]
bic r3, r3, #FMsk(MSC_RT)
bic r3, r3, #FMsk(MSC_RT)<<16
ldr r3, [r0]
bic r3, r3, #FMsk(MSC_RT)
bic r3, r3, #FMsk(MSC_RT)<<16
ldr r4, [r1]
bic r4, r4, #FMsk(MSC_RT)
bic r4, r4, #FMsk(MSC_RT)<<16
ldr r4, [r1]
bic r4, r4, #FMsk(MSC_RT)
bic r4, r4, #FMsk(MSC_RT)<<16
ldr r5, [r2]
bic r5, r5, #FMsk(MSC_RT)
bic r5, r5, #FMsk(MSC_RT)<<16
ldr r5, [r2]
bic r5, r5, #FMsk(MSC_RT)
bic r5, r5, #FMsk(MSC_RT)<<16
ldr r6, =MDREFR
ldr r6, =MDREFR
ldr r7, [r6]
bic r7, r7, #0x0000FF00
bic r7, r7, #0x000000F0
orr r8, r7, #MDREFR_SLFRSH
ldr r7, [r6]
bic r7, r7, #0x0000FF00
bic r7, r7, #0x000000F0
orr r8, r7, #MDREFR_SLFRSH
ldr r9, =MDCNFG
ldr r10, [r9]
bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
ldr r9, =MDCNFG
ldr r10, [r9]
bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
bic r11, r8, #MDREFR_SLFRSH
bic r11, r11, #MDREFR_E1PIN
bic r11, r8, #MDREFR_SLFRSH
bic r11, r11, #MDREFR_E1PIN
ldr r12, =PMCR
ldr r12, =PMCR
mov r13, #PMCR_SF
mov r13, #PMCR_SF
b sa1110_sdram_controller_fix
@@ -188,10 +188,10 @@ ENTRY(sa1100_cpu_resume)
mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
mcr p15, 0, r4, c3, c0, 0 @ domain ID
mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
mcr p15, 0, r4, c3, c0, 0 @ domain ID
mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
mcr p15, 0, r6, c13, c0, 0 @ PID
b resume_turn_on_mmu @ cache align execution
@@ -209,7 +209,7 @@ sleep_save_sp:
.text
resume_after_mmu:
mcr p15, 0, r1, c15, c1, 2 @ enable clock switching
mcr p15, 0, r1, c15, c1, 2 @ enable clock switching
ldmfd sp!, {r4 - r12, pc} @ return to caller

2
arch/arm/mach-sa1100/time.c
View File

@@ -2,7 +2,7 @@
* linux/arch/arm/mach-sa1100/time.c
*
* Copyright (C) 1998 Deborah Wallach.
* Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
* Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
*
* 2000/03/29 (C) Nicolas Pitre <nico@cam.org>
* Rewritten: big cleanup, much simpler, better HZ accuracy.