[PATCH] sky2: yukon-ec-u chipset initialization
Add more complete setup code for Yukon EC_U chipset. Based on matching code in 8.31 code in SysKonnect vendor driver. Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
This commit is contained in:
committed by
Francois Romieu
parent
c45ec65660
commit
977bdf06ca
@@ -232,7 +232,17 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
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if (hw->ports > 1)
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reg1 |= PCI_Y2_PHY2_COMA;
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}
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if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
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pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
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pci_read_config_dword(hw->pdev, PCI_DEV_REG4, ®1);
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reg1 &= P_ASPM_CONTROL_MSK;
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pci_write_config_dword(hw->pdev, PCI_DEV_REG4, reg1);
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pci_write_config_dword(hw->pdev, PCI_DEV_REG5, 0);
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}
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pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
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break;
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case PCI_D3hot:
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@@ -463,16 +473,31 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
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}
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
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/* apply fixes in PHY AFE */
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gm_phy_write(hw, port, 22, 255);
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/* increase differential signal amplitude in 10BASE-T */
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gm_phy_write(hw, port, 24, 0xaa99);
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gm_phy_write(hw, port, 23, 0x2011);
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/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
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gm_phy_write(hw, port, 24, 0xa204);
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gm_phy_write(hw, port, 23, 0x2002);
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/* set page register to 0 */
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gm_phy_write(hw, port, 22, 0);
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} else {
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
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if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
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/* turn on 100 Mbps LED (LED_LINK100) */
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ledover |= PHY_M_LED_MO_100(MO_LED_ON);
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}
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if (ledover)
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gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
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if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
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/* turn on 100 Mbps LED (LED_LINK100) */
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ledover |= PHY_M_LED_MO_100(MO_LED_ON);
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}
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if (ledover)
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gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
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/* Enable phy interrupt on auto-negotiation complete (or link up) */
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if (sky2->autoneg == AUTONEG_ENABLE)
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gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
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@@ -953,6 +978,12 @@ static int sky2_rx_start(struct sky2_port *sky2)
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sky2->rx_put = sky2->rx_next = 0;
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sky2_qset(hw, rxq);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
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/* MAC Rx RAM Read is controlled by hardware */
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sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
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}
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sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
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rx_set_checksum(sky2);
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@@ -1035,9 +1066,10 @@ static int sky2_up(struct net_device *dev)
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RB_RST_SET);
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sky2_qset(hw, txqaddr[port]);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U)
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sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
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/* Set almost empty threshold */
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if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
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sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
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sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
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TX_RING_SIZE - 1);
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