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[SPARC64]: Use 13-bit context size always.

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We no longer have the problems that require using the smaller
sizes.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2006-02-26 20:37:41 -08:00
committed by David S. Miller
parent 7a591cfe4e
commit 97c4b6f95a
1 changed files with 1 additions and 13 deletions
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14
include/asm-sparc64/mmu.h
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@@ -6,19 +6,7 @@
#include <asm/const.h> #include <asm/const.h>
#include <asm/hypervisor.h> #include <asm/hypervisor.h>
/* #define CTX_NR_BITS 13
* For the 8k pagesize kernel, use only 10 hw context bits to optimize some
* shifts in the fast tlbmiss handlers, instead of all 13 bits (specifically
* for vpte offset calculation). For other pagesizes, this optimization in
* the tlbhandlers can not be done; but still, all 13 bits can not be used
* because the tlb handlers use "andcc" instruction which sign extends 13
* bit arguments.
*/
#if PAGE_SHIFT == 13
#define CTX_NR_BITS 10
#else
#define CTX_NR_BITS 12
#endif
#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL)) #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))