[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle
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b6ec8f069b
commit
97dcb82de6
@@ -47,9 +47,9 @@ extern asmlinkage void excite_handle_int(void);
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*/
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init(0);
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rm7k_cpu_irq_init(8);
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rm9k_cpu_irq_init(12);
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mips_cpu_irq_init();
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rm7k_cpu_irq_init();
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rm9k_cpu_irq_init();
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#ifdef CONFIG_KGDB
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excite_kgdb_init();
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