[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle
parent
b6ec8f069b
commit
97dcb82de6
@ -18,16 +18,14 @@
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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static int irq_base;
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static inline void unmask_rm9k_irq(unsigned int irq)
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{
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set_c0_intcontrol(0x1000 << (irq - irq_base));
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set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
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}
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static inline void mask_rm9k_irq(unsigned int irq)
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{
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clear_c0_intcontrol(0x1000 << (irq - irq_base));
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clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
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}
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static inline void rm9k_cpu_irq_enable(unsigned int irq)
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@ -93,8 +91,9 @@ unsigned int rm9000_perfcount_irq;
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EXPORT_SYMBOL(rm9000_perfcount_irq);
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void __init rm9k_cpu_irq_init(int base)
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void __init rm9k_cpu_irq_init(void)
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{
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int base = RM9K_CPU_IRQ_BASE;
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int i;
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clear_c0_intcontrol(0x0000f000); /* Mask all */
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@ -106,6 +105,4 @@ void __init rm9k_cpu_irq_init(int base)
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rm9000_perfcount_irq = base + 1;
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set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
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handle_level_irq);
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irq_base = base;
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}
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