ACPI: Processor native C-states using MWAIT
Intel processors starting with the Core Duo support support processor native C-state using the MWAIT instruction. Refer: Intel Architecture Software Developer's Manual http://www.intel.com/design/Pentium4/manuals/253668.htm Platform firmware exports the support for Native C-state to OS using ACPI _PDC and _CST methods. Refer: Intel Processor Vendor-Specific ACPI: Interface Specification http://www.intel.com/technology/iapc/acpi/downloads/302223.htm With Processor Native C-state, we use 'MWAIT' instruction on the processor to enter different C-states (C1, C2, C3). We won't use the special IO ports to enter C-state and no SMM mode etc required to enter C-state. Overall this will mean better C-state support. One major advantage of using MWAIT for all C-states is, with this and "treat interrupt as break event" feature of MWAIT, we can now get accurate timing for the time spent in C1, C2, .. states. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Len Brown <len.brown@intel.com>
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Len Brown
parent
b4bd8c6643
commit
991528d734
@@ -219,6 +219,23 @@ static void acpi_safe_halt(void)
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static atomic_t c3_cpu_count;
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/* Common C-state entry for C2, C3, .. */
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static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
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{
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if (cstate->space_id == ACPI_CSTATE_FFH) {
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/* Call into architectural FFH based C-state */
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acpi_processor_ffh_cstate_enter(cstate);
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} else {
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int unused;
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/* IO port based C-state */
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inb(cstate->address);
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/* Dummy wait op - must do something useless after P_LVL2 read
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because chipsets cannot guarantee that STPCLK# signal
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gets asserted in time to freeze execution properly. */
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unused = inl(acpi_fadt.xpm_tmr_blk.address);
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}
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}
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static void acpi_processor_idle(void)
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{
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struct acpi_processor *pr = NULL;
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@@ -361,11 +378,7 @@ static void acpi_processor_idle(void)
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/* Get start time (ticks) */
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t1 = inl(acpi_fadt.xpm_tmr_blk.address);
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/* Invoke C2 */
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inb(cx->address);
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/* Dummy wait op - must do something useless after P_LVL2 read
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because chipsets cannot guarantee that STPCLK# signal
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gets asserted in time to freeze execution properly. */
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t2 = inl(acpi_fadt.xpm_tmr_blk.address);
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acpi_cstate_enter(cx);
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/* Get end time (ticks) */
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t2 = inl(acpi_fadt.xpm_tmr_blk.address);
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@@ -401,9 +414,7 @@ static void acpi_processor_idle(void)
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/* Get start time (ticks) */
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t1 = inl(acpi_fadt.xpm_tmr_blk.address);
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/* Invoke C3 */
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inb(cx->address);
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/* Dummy wait op (see above) */
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t2 = inl(acpi_fadt.xpm_tmr_blk.address);
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acpi_cstate_enter(cx);
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/* Get end time (ticks) */
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t2 = inl(acpi_fadt.xpm_tmr_blk.address);
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if (pr->flags.bm_check) {
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@@ -628,20 +639,16 @@ static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
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return 0;
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}
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static int acpi_processor_get_power_info_default_c1(struct acpi_processor *pr)
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static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
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{
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/* Zero initialize all the C-states info. */
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memset(pr->power.states, 0, sizeof(pr->power.states));
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/* set the first C-State to C1 */
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pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
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/* the C0 state only exists as a filler in our array,
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* and all processors need to support C1 */
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if (!pr->power.states[ACPI_STATE_C1].valid) {
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/* set the first C-State to C1 */
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/* all processors need to support C1 */
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pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
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pr->power.states[ACPI_STATE_C1].valid = 1;
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}
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/* the C0 state only exists as a filler in our array */
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pr->power.states[ACPI_STATE_C0].valid = 1;
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pr->power.states[ACPI_STATE_C1].valid = 1;
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return 0;
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}
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@@ -658,12 +665,7 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
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if (nocst)
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return -ENODEV;
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current_count = 1;
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/* Zero initialize C2 onwards and prepare for fresh CST lookup */
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for (i = 2; i < ACPI_PROCESSOR_MAX_POWER; i++)
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memset(&(pr->power.states[i]), 0,
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sizeof(struct acpi_processor_cx));
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current_count = 0;
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status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
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if (ACPI_FAILURE(status)) {
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@@ -718,22 +720,39 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
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(reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
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continue;
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cx.address = (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) ?
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0 : reg->address;
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/* There should be an easy way to extract an integer... */
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obj = (union acpi_object *)&(element->package.elements[1]);
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if (obj->type != ACPI_TYPE_INTEGER)
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continue;
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cx.type = obj->integer.value;
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/*
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* Some buggy BIOSes won't list C1 in _CST -
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* Let acpi_processor_get_power_info_default() handle them later
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*/
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if (i == 1 && cx.type != ACPI_STATE_C1)
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current_count++;
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if ((cx.type != ACPI_STATE_C1) &&
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(reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO))
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continue;
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cx.address = reg->address;
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cx.index = current_count + 1;
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if ((cx.type < ACPI_STATE_C2) || (cx.type > ACPI_STATE_C3))
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continue;
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cx.space_id = ACPI_CSTATE_SYSTEMIO;
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if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
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if (acpi_processor_ffh_cstate_probe
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(pr->id, &cx, reg) == 0) {
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cx.space_id = ACPI_CSTATE_FFH;
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} else if (cx.type != ACPI_STATE_C1) {
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/*
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* C1 is a special case where FIXED_HARDWARE
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* can be handled in non-MWAIT way as well.
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* In that case, save this _CST entry info.
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* That is, we retain space_id of SYSTEM_IO for
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* halt based C1.
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* Otherwise, ignore this info and continue.
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*/
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continue;
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}
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}
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obj = (union acpi_object *)&(element->package.elements[2]);
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if (obj->type != ACPI_TYPE_INTEGER)
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@@ -938,12 +957,18 @@ static int acpi_processor_get_power_info(struct acpi_processor *pr)
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/* NOTE: the idle thread may not be running while calling
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* this function */
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/* Adding C1 state */
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acpi_processor_get_power_info_default_c1(pr);
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/* Zero initialize all the C-states info. */
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memset(pr->power.states, 0, sizeof(pr->power.states));
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result = acpi_processor_get_power_info_cst(pr);
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if (result == -ENODEV)
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acpi_processor_get_power_info_fadt(pr);
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if (result)
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return result;
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acpi_processor_get_power_info_default(pr);
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pr->power.count = acpi_processor_power_verify(pr);
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/*
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