[PATCH] Alpha: ISA IRQs fixup for dp264
Basically, this extends original dp264 fixup to all dp264 variations. Here is one minor change: mask out bits 4-7 of a value assigned by SRM, because - newer consoles report ISA IRQs with offset 0xe0; - even if console IRQ value is bogus, we'll have a value < 16 so it should be harmless as it won't clash with native IRQs. Particularly this fixes USB interrupt problem on xp1000 and es40. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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committed by
Linus Torvalds
parent
044a500e46
commit
997a51ae37
@@ -394,6 +394,22 @@ clipper_init_irq(void)
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* 10 64 bit PCI option slot 3 (not bus 0)
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* 10 64 bit PCI option slot 3 (not bus 0)
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*/
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*/
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static int __init
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isa_irq_fixup(struct pci_dev *dev, int irq)
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{
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u8 irq8;
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if (irq > 0)
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return irq;
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/* This interrupt is routed via ISA bridge, so we'll
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just have to trust whatever value the console might
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have assigned. */
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
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return irq8 & 0xf;
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}
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static int __init
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static int __init
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dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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{
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@@ -407,25 +423,13 @@ dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{ 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
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{ 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
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};
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};
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const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
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const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
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struct pci_controller *hose = dev->sysdata;
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struct pci_controller *hose = dev->sysdata;
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int irq = COMMON_TABLE_LOOKUP;
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int irq = COMMON_TABLE_LOOKUP;
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if (irq > 0) {
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if (irq > 0)
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irq += 16 * hose->index;
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irq += 16 * hose->index;
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} else {
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/* ??? The Contaq IDE controller on the ISA bridge uses
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"legacy" interrupts 14 and 15. I don't know if anything
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can wind up at the same slot+pin on hose1, so we'll
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just have to trust whatever value the console might
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have assigned. */
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u8 irq8;
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return isa_irq_fixup(dev, irq);
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
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irq = irq8;
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}
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return irq;
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}
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}
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static int __init
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static int __init
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@@ -453,7 +457,8 @@ monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{ 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
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{ 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
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};
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};
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const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
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const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
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}
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}
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static u8 __init
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static u8 __init
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@@ -507,7 +512,8 @@ webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{ 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
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{ 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
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};
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};
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const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
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const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
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}
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}
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static int __init
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static int __init
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@@ -524,14 +530,13 @@ clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{ -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
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{ -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
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};
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};
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const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
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const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
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struct pci_controller *hose = dev->sysdata;
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struct pci_controller *hose = dev->sysdata;
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int irq = COMMON_TABLE_LOOKUP;
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int irq = COMMON_TABLE_LOOKUP;
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if (irq > 0)
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if (irq > 0)
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irq += 16 * hose->index;
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irq += 16 * hose->index;
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return irq;
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return isa_irq_fixup(dev, irq);
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}
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}
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static void __init
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static void __init
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