lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

[PATCH] m32r: Fix M32104 cache flushing routines

Browse Source 
This patch fixes cache memory parameter setting for the M32104 target.  So
far, its performance seemed to have been degraded due to incorrect cache
parameter setting.

  * arch/m32r/boot/setup.S: Set SFR(Special Fuction Registers) region
    to be non-cachable explicitly.
  * arch/m32r/mm/cache.c: Fix cache flushing routines not to switch off
    the M32104 cache.

Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Hirokazu Takata
2006-01-06 00:18:44 -08:00
committed by Linus Torvalds
parent 46ea178b7a
commit 9b791d4766
2 changed files with 33 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
arch/m32r/boot/setup.S
View File

@@ -1,11 +1,10 @@
/*
* linux/arch/m32r/boot/setup.S -- A setup code.
*
* Copyright (C) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
* and Hitoshi Yamamoto
* Copyright (C) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto, Hayato Fujiwara
*
*/
/* $Id$ */
#include <linux/linkage.h>
#include <asm/segment.h>
@@ -81,6 +80,16 @@ ENTRY(boot)
; ldi r1, #0x00 ; cache off
st r1, @r0
#elif defined(CONFIG_CHIP_M32104)
ldi r0, #-96 ; DNCR0
seth r1, #0x0060 ; from 0x00600000
or3 r1, r1, #0x0005 ; size 2MB
st r1, @r0
seth r1, #0x0100 ; from 0x01000000
or3 r1, r1, #0x0003 ; size 16MB
st r1, @+r0
seth r1, #0x0200 ; from 0x02000000
or3 r1, r1, #0x0002 ; size 32MB
st r1, @+r0
ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
ldi r1, #0x703 ; cache on (with invalidation)
st r1, @r0