MIPS: Alchemy: devboard register abstraction
All Alchemy development boards have external CPLDs with a few registers in them. They all share an identical register layout with only a few minor differences (except the PB1000) in bit functions and base addresses. This patch - adds a primitive facility to initialize and use these external registers, - replaces all occurrences of bcsr->xxx accesses with calls to the new functions (the pb1200 cascade irq handling code is special). - collects BCSR register information scattered throughout the board headers in a central place. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
committed by
Ralf Baechle
Ralf Baechle
parent
ebc89718a4
commit
9bdcf336d0
235
arch/mips/include/asm/mach-db1x00/bcsr.h
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235
arch/mips/include/asm/mach-db1x00/bcsr.h
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@ -0,0 +1,235 @@
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/*
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* bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
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*
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* All Alchemy development boards (except, of course, the weird PB1000)
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* have a few registers in a CPLD with standardised layout; they mostly
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* only differ in base address and bit meanings in the RESETS and BOARD
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* registers.
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*
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* All data taken from the official AMD board documentation sheets.
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*/
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#ifndef _DB1XXX_BCSR_H_
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#define _DB1XXX_BCSR_H_
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/* BCSR base addresses on various boards. BCSR base 2 refers to the
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* physical address of the first HEXLEDS register, which is usually
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* a variable offset from the WHOAMI register.
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*/
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/* DB1000, DB1100, DB1500, PB1100, PB1500 */
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#define DB1000_BCSR_PHYS_ADDR 0x0E000000
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#define DB1000_BCSR_HEXLED_OFS 0x01000000
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#define DB1550_BCSR_PHYS_ADDR 0x0F000000
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#define DB1550_BCSR_HEXLED_OFS 0x00400000
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#define PB1550_BCSR_PHYS_ADDR 0x0F000000
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#define PB1550_BCSR_HEXLED_OFS 0x00800000
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#define DB1200_BCSR_PHYS_ADDR 0x19800000
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#define DB1200_BCSR_HEXLED_OFS 0x00400000
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#define PB1200_BCSR_PHYS_ADDR 0x0D800000
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#define PB1200_BCSR_HEXLED_OFS 0x00400000
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enum bcsr_id {
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/* BCSR base 1 */
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BCSR_WHOAMI = 0,
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BCSR_STATUS,
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BCSR_SWITCHES,
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BCSR_RESETS,
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BCSR_PCMCIA,
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BCSR_BOARD,
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BCSR_LEDS,
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BCSR_SYSTEM,
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/* Au1200/1300 based boards */
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BCSR_INTCLR,
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BCSR_INTSET,
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BCSR_MASKCLR,
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BCSR_MASKSET,
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BCSR_SIGSTAT,
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BCSR_INTSTAT,
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/* BCSR base 2 */
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BCSR_HEXLEDS,
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BCSR_RSVD1,
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BCSR_HEXCLEAR,
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BCSR_CNT,
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};
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/* register offsets, valid for all Db1xxx/Pb1xxx boards */
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#define BCSR_REG_WHOAMI 0x00
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#define BCSR_REG_STATUS 0x04
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#define BCSR_REG_SWITCHES 0x08
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#define BCSR_REG_RESETS 0x0c
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#define BCSR_REG_PCMCIA 0x10
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#define BCSR_REG_BOARD 0x14
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#define BCSR_REG_LEDS 0x18
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#define BCSR_REG_SYSTEM 0x1c
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/* Au1200/Au1300 based boards: CPLD IRQ muxer */
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#define BCSR_REG_INTCLR 0x20
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#define BCSR_REG_INTSET 0x24
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#define BCSR_REG_MASKCLR 0x28
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#define BCSR_REG_MASKSET 0x2c
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#define BCSR_REG_SIGSTAT 0x30
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#define BCSR_REG_INTSTAT 0x34
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/* hexled control, offset from BCSR base 2 */
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#define BCSR_REG_HEXLEDS 0x00
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#define BCSR_REG_HEXCLEAR 0x08
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/*
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* Register Bits and Pieces.
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*/
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#define BCSR_WHOAMI_DCID(x) ((x) & 0xf)
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#define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf)
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#define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf)
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/* register "WHOAMI" bits 11:8 identify the board */
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enum bcsr_whoami_boards {
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BCSR_WHOAMI_PB1500 = 1,
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BCSR_WHOAMI_PB1500R2,
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BCSR_WHOAMI_PB1100,
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BCSR_WHOAMI_DB1000,
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BCSR_WHOAMI_DB1100,
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BCSR_WHOAMI_DB1500,
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BCSR_WHOAMI_DB1550,
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BCSR_WHOAMI_PB1550_DDR,
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BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR,
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BCSR_WHOAMI_PB1550_SDR,
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BCSR_WHOAMI_PB1200_DDR1,
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BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
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BCSR_WHOAMI_PB1200_DDR2,
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BCSR_WHOAMI_DB1200,
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};
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/* STATUS reg. Unless otherwise noted, they're valid on all boards.
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* PB1200 = DB1200.
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*/
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#define BCSR_STATUS_PC0VS 0x0003
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#define BCSR_STATUS_PC1VS 0x000C
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#define BCSR_STATUS_PC0FI 0x0010
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#define BCSR_STATUS_PC1FI 0x0020
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#define BCSR_STATUS_PB1550_SWAPBOOT 0x0040
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#define BCSR_STATUS_SRAMWIDTH 0x0080
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#define BCSR_STATUS_FLASHBUSY 0x0100
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#define BCSR_STATUS_ROMBUSY 0x0400
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#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */
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#define BCSR_STATUS_SD1WP 0x0800
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#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
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#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
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#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */
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#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */
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#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
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#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
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#define BCSR_STATUS_FLASHDEN 0xC000
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#define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */
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#define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */
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#define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */
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#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
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#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
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/* DB/PB1000,1100,1500,1550 */
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#define BCSR_RESETS_PHY0 0x0001
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#define BCSR_RESETS_PHY1 0x0002
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#define BCSR_RESETS_DC 0x0004
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#define BCSR_RESETS_FIR_SEL 0x2000
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#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
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#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
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#define BCSR_RESETS_PB1550_WSCFSM 0x2000
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#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
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#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
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#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
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#define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */
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#define BCSR_BOARD_PCIM66EN 0x0001
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#define BCSR_BOARD_SD0PWR 0x0040
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#define BCSR_BOARD_SD1PWR 0x0080
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#define BCSR_BOARD_PCIM33 0x0100
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#define BCSR_BOARD_PCIEXTARB 0x0200
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#define BCSR_BOARD_GPIO200RST 0x0400
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#define BCSR_BOARD_PCICLKOUT 0x0800
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#define BCSR_BOARD_PCICFG 0x1000
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#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */
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#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
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#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
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/* DB/PB1200 */
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#define BCSR_RESETS_ETH 0x0001
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#define BCSR_RESETS_CAMERA 0x0002
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#define BCSR_RESETS_DC 0x0004
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#define BCSR_RESETS_IDE 0x0008
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#define BCSR_RESETS_TV 0x0010 /* DB1200 */
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/* Not resets but in the same register */
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#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
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#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
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#define BCSR_RESETS_PSC0MUX 0x1000
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#define BCSR_RESETS_PSC1MUX 0x2000
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#define BCSR_RESETS_SPISEL 0x4000
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#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
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#define BCSR_BOARD_LCDVEE 0x0001
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#define BCSR_BOARD_LCDVDD 0x0002
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#define BCSR_BOARD_LCDBL 0x0004
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#define BCSR_BOARD_CAMSNAP 0x0010
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#define BCSR_BOARD_CAMPWR 0x0020
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#define BCSR_BOARD_SD0PWR 0x0040
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#define BCSR_SWITCHES_DIP 0x00FF
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#define BCSR_SWITCHES_DIP_1 0x0080
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#define BCSR_SWITCHES_DIP_2 0x0040
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#define BCSR_SWITCHES_DIP_3 0x0020
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#define BCSR_SWITCHES_DIP_4 0x0010
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#define BCSR_SWITCHES_DIP_5 0x0008
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#define BCSR_SWITCHES_DIP_6 0x0004
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#define BCSR_SWITCHES_DIP_7 0x0002
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#define BCSR_SWITCHES_DIP_8 0x0001
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#define BCSR_SWITCHES_ROTARY 0x0F00
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#define BCSR_PCMCIA_PC0VPP 0x0003
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#define BCSR_PCMCIA_PC0VCC 0x000C
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#define BCSR_PCMCIA_PC0DRVEN 0x0010
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#define BCSR_PCMCIA_PC0RST 0x0080
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#define BCSR_PCMCIA_PC1VPP 0x0300
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#define BCSR_PCMCIA_PC1VCC 0x0C00
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#define BCSR_PCMCIA_PC1DRVEN 0x1000
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#define BCSR_PCMCIA_PC1RST 0x8000
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#define BCSR_LEDS_DECIMALS 0x0003
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#define BCSR_LEDS_LED0 0x0100
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#define BCSR_LEDS_LED1 0x0200
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#define BCSR_LEDS_LED2 0x0400
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#define BCSR_LEDS_LED3 0x0800
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#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
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#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
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#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
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/* initialize BCSR for a board. Provide the PHYSICAL addresses of both
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* BCSR spaces.
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*/
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void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys);
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/* read a board register */
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unsigned short bcsr_read(enum bcsr_id reg);
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/* write to a board register */
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void bcsr_write(enum bcsr_id reg, unsigned short val);
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/* modify a register. clear bits set in 'clr', set bits set in 'set' */
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void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set);
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#endif
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@ -45,113 +45,6 @@
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define I2S_PSC_BASE PSC1_BASE_ADDR
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#define BCSR_KSEG1_ADDR 0xB9800000
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typedef volatile struct
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{
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/*00*/ u16 whoami;
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u16 reserved0;
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/*04*/ u16 status;
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u16 reserved1;
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/*08*/ u16 switches;
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u16 reserved2;
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/*0C*/ u16 resets;
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u16 reserved3;
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/*10*/ u16 pcmcia;
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u16 reserved4;
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/*14*/ u16 board;
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u16 reserved5;
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/*18*/ u16 disk_leds;
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u16 reserved6;
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/*1C*/ u16 system;
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u16 reserved7;
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/*20*/ u16 intclr;
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u16 reserved8;
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/*24*/ u16 intset;
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u16 reserved9;
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/*28*/ u16 intclr_mask;
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u16 reserved10;
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/*2C*/ u16 intset_mask;
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u16 reserved11;
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/*30*/ u16 sig_status;
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u16 reserved12;
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/*34*/ u16 int_status;
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u16 reserved13;
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/*38*/ u16 reserved14;
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u16 reserved15;
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/*3C*/ u16 reserved16;
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u16 reserved17;
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} BCSR;
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static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
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/*
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* Register bit definitions for the BCSRs
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*/
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#define BCSR_WHOAMI_DCID 0x000F
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#define BCSR_WHOAMI_CPLD 0x00F0
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#define BCSR_WHOAMI_BOARD 0x0F00
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#define BCSR_STATUS_PCMCIA0VS 0x0003
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#define BCSR_STATUS_PCMCIA1VS 0x000C
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#define BCSR_STATUS_SWAPBOOT 0x0040
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#define BCSR_STATUS_FLASHBUSY 0x0100
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#define BCSR_STATUS_IDECBLID 0x0200
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#define BCSR_STATUS_SD0WP 0x0400
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#define BCSR_STATUS_U0RXD 0x1000
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#define BCSR_STATUS_U1RXD 0x2000
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#define BCSR_SWITCHES_OCTAL 0x00FF
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#define BCSR_SWITCHES_DIP_1 0x0080
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#define BCSR_SWITCHES_DIP_2 0x0040
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#define BCSR_SWITCHES_DIP_3 0x0020
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#define BCSR_SWITCHES_DIP_4 0x0010
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#define BCSR_SWITCHES_DIP_5 0x0008
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#define BCSR_SWITCHES_DIP_6 0x0004
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#define BCSR_SWITCHES_DIP_7 0x0002
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#define BCSR_SWITCHES_DIP_8 0x0001
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#define BCSR_SWITCHES_ROTARY 0x0F00
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#define BCSR_RESETS_ETH 0x0001
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#define BCSR_RESETS_CAMERA 0x0002
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#define BCSR_RESETS_DC 0x0004
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#define BCSR_RESETS_IDE 0x0008
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#define BCSR_RESETS_TV 0x0010
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/* Not resets but in the same register */
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#define BCSR_RESETS_PWMR1MUX 0x0800
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#define BCSR_RESETS_PCS0MUX 0x1000
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#define BCSR_RESETS_PCS1MUX 0x2000
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#define BCSR_RESETS_SPISEL 0x4000
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#define BCSR_PCMCIA_PC0VPP 0x0003
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#define BCSR_PCMCIA_PC0VCC 0x000C
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#define BCSR_PCMCIA_PC0DRVEN 0x0010
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#define BCSR_PCMCIA_PC0RST 0x0080
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#define BCSR_PCMCIA_PC1VPP 0x0300
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#define BCSR_PCMCIA_PC1VCC 0x0C00
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#define BCSR_PCMCIA_PC1DRVEN 0x1000
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#define BCSR_PCMCIA_PC1RST 0x8000
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#define BCSR_BOARD_LCDVEE 0x0001
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#define BCSR_BOARD_LCDVDD 0x0002
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#define BCSR_BOARD_LCDBL 0x0004
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#define BCSR_BOARD_CAMSNAP 0x0010
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#define BCSR_BOARD_CAMPWR 0x0020
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#define BCSR_BOARD_SD0PWR 0x0040
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#define BCSR_LEDS_DECIMALS 0x0003
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#define BCSR_LEDS_LED0 0x0100
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#define BCSR_LEDS_LED1 0x0200
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#define BCSR_LEDS_LED2 0x0400
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#define BCSR_LEDS_LED3 0x0800
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#define BCSR_SYSTEM_POWEROFF 0x4000
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#define BCSR_SYSTEM_RESET 0x8000
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/* Bit positions for the different interrupt sources */
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#define BCSR_INT_IDE 0x0001
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#define BCSR_INT_ETH 0x0002
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@ -222,7 +115,7 @@ enum external_pb1200_ints {
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#define BOARD_PC0_INT DB1200_PC0_INT
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#define BOARD_PC1_INT DB1200_PC1_INT
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#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
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#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET))))
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/* NAND chip select */
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#define NAND_CS 1
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@ -41,102 +41,10 @@
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#define SMBUS_PSC_BASE PSC2_BASE_ADDR
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#define I2S_PSC_BASE PSC3_BASE_ADDR
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#define BCSR_KSEG1_ADDR 0xAF000000
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#define NAND_PHYS_ADDR 0x20000000
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#else
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#define BCSR_KSEG1_ADDR 0xAE000000
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#endif
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/*
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* Overlay data structure of the DBAu1x00 board registers.
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* Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
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*/
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typedef volatile struct
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{
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/*00*/ unsigned short whoami;
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unsigned short reserved0;
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/*04*/ unsigned short status;
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unsigned short reserved1;
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/*08*/ unsigned short switches;
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unsigned short reserved2;
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/*0C*/ unsigned short resets;
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unsigned short reserved3;
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/*10*/ unsigned short pcmcia;
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unsigned short reserved4;
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/*14*/ unsigned short specific;
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unsigned short reserved5;
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/*18*/ unsigned short leds;
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unsigned short reserved6;
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/*1C*/ unsigned short swreset;
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unsigned short reserved7;
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} BCSR;
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/*
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* Register/mask bit definitions for the BCSRs
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*/
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#define BCSR_WHOAMI_DCID 0x000F
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#define BCSR_WHOAMI_CPLD 0x00F0
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#define BCSR_WHOAMI_BOARD 0x0F00
|
||||
|
||||
#define BCSR_STATUS_PC0VS 0x0003
|
||||
#define BCSR_STATUS_PC1VS 0x000C
|
||||
#define BCSR_STATUS_PC0FI 0x0010
|
||||
#define BCSR_STATUS_PC1FI 0x0020
|
||||
#define BCSR_STATUS_FLASHBUSY 0x0100
|
||||
#define BCSR_STATUS_ROMBUSY 0x0400
|
||||
#define BCSR_STATUS_SWAPBOOT 0x2000
|
||||
#define BCSR_STATUS_FLASHDEN 0xC000
|
||||
|
||||
#define BCSR_SWITCHES_DIP 0x00FF
|
||||
#define BCSR_SWITCHES_DIP_1 0x0080
|
||||
#define BCSR_SWITCHES_DIP_2 0x0040
|
||||
#define BCSR_SWITCHES_DIP_3 0x0020
|
||||
#define BCSR_SWITCHES_DIP_4 0x0010
|
||||
#define BCSR_SWITCHES_DIP_5 0x0008
|
||||
#define BCSR_SWITCHES_DIP_6 0x0004
|
||||
#define BCSR_SWITCHES_DIP_7 0x0002
|
||||
#define BCSR_SWITCHES_DIP_8 0x0001
|
||||
#define BCSR_SWITCHES_ROTARY 0x0F00
|
||||
|
||||
#define BCSR_RESETS_PHY0 0x0001
|
||||
#define BCSR_RESETS_PHY1 0x0002
|
||||
#define BCSR_RESETS_DC 0x0004
|
||||
#define BCSR_RESETS_FIR_SEL 0x2000
|
||||
#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
|
||||
#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
|
||||
#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
|
||||
#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
|
||||
#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
|
||||
|
||||
#define BCSR_PCMCIA_PC0VPP 0x0003
|
||||
#define BCSR_PCMCIA_PC0VCC 0x000C
|
||||
#define BCSR_PCMCIA_PC0DRVEN 0x0010
|
||||
#define BCSR_PCMCIA_PC0RST 0x0080
|
||||
#define BCSR_PCMCIA_PC1VPP 0x0300
|
||||
#define BCSR_PCMCIA_PC1VCC 0x0C00
|
||||
#define BCSR_PCMCIA_PC1DRVEN 0x1000
|
||||
#define BCSR_PCMCIA_PC1RST 0x8000
|
||||
|
||||
#define BCSR_BOARD_PCIM66EN 0x0001
|
||||
#define BCSR_BOARD_SD0_PWR 0x0040
|
||||
#define BCSR_BOARD_SD1_PWR 0x0080
|
||||
#define BCSR_BOARD_PCIM33 0x0100
|
||||
#define BCSR_BOARD_GPIO200RST 0x0400
|
||||
#define BCSR_BOARD_PCICFG 0x1000
|
||||
#define BCSR_BOARD_SD0_WP 0x4000
|
||||
#define BCSR_BOARD_SD1_WP 0x8000
|
||||
|
||||
#define BCSR_LEDS_DECIMALS 0x0003
|
||||
#define BCSR_LEDS_LED0 0x0100
|
||||
#define BCSR_LEDS_LED1 0x0200
|
||||
#define BCSR_LEDS_LED2 0x0400
|
||||
#define BCSR_LEDS_LED3 0x0800
|
||||
|
||||
#define BCSR_SWRESET_RESET 0x0080
|
||||
|
||||
/* PCMCIA DBAu1x00 specific defines */
|
||||
#define PCMCIA_MAX_SOCK 1
|
||||
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
|
||||
|
||||
Reference in New Issue
Block a user