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MIPS: Alchemy: devboard register abstraction

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All Alchemy development boards have external CPLDs with a few registers
in them.  They all share an identical register layout with only a few
minor differences (except the PB1000) in bit functions and base
addresses.

This patch
- adds a primitive facility to initialize and use these external
  registers,
- replaces all occurrences of bcsr->xxx accesses with calls to the new
  functions (the pb1200 cascade irq handling code is special).
- collects BCSR register information scattered throughout the board
  headers in a central place.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
2009-10-04 14:55:24 +02:00
committed by Ralf Baechle
parent ebc89718a4
commit 9bdcf336d0
19 changed files with 475 additions and 596 deletions
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109
arch/mips/include/asm/mach-db1x00/db1200.h
View File

@@ -45,113 +45,6 @@
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
#define BCSR_KSEG1_ADDR 0xB9800000
typedef volatile struct
{
/*00*/ u16 whoami;
u16 reserved0;
/*04*/ u16 status;
u16 reserved1;
/*08*/ u16 switches;
u16 reserved2;
/*0C*/ u16 resets;
u16 reserved3;
/*10*/ u16 pcmcia;
u16 reserved4;
/*14*/ u16 board;
u16 reserved5;
/*18*/ u16 disk_leds;
u16 reserved6;
/*1C*/ u16 system;
u16 reserved7;
/*20*/ u16 intclr;
u16 reserved8;
/*24*/ u16 intset;
u16 reserved9;
/*28*/ u16 intclr_mask;
u16 reserved10;
/*2C*/ u16 intset_mask;
u16 reserved11;
/*30*/ u16 sig_status;
u16 reserved12;
/*34*/ u16 int_status;
u16 reserved13;
/*38*/ u16 reserved14;
u16 reserved15;
/*3C*/ u16 reserved16;
u16 reserved17;
} BCSR;
static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
/*
* Register bit definitions for the BCSRs
*/
#define BCSR_WHOAMI_DCID 0x000F
#define BCSR_WHOAMI_CPLD 0x00F0
#define BCSR_WHOAMI_BOARD 0x0F00
#define BCSR_STATUS_PCMCIA0VS 0x0003
#define BCSR_STATUS_PCMCIA1VS 0x000C
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
#define BCSR_SWITCHES_DIP_2 0x0040
#define BCSR_SWITCHES_DIP_3 0x0020
#define BCSR_SWITCHES_DIP_4 0x0010
#define BCSR_SWITCHES_DIP_5 0x0008
#define BCSR_SWITCHES_DIP_6 0x0004
#define BCSR_SWITCHES_DIP_7 0x0002
#define BCSR_SWITCHES_DIP_8 0x0001
#define BCSR_SWITCHES_ROTARY 0x0F00
#define BCSR_RESETS_ETH 0x0001
#define BCSR_RESETS_CAMERA 0x0002
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
#define BCSR_RESETS_TV 0x0010
/* Not resets but in the same register */
#define BCSR_RESETS_PWMR1MUX 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
#define BCSR_PCMCIA_PC0VPP 0x0003
#define BCSR_PCMCIA_PC0VCC 0x000C
#define BCSR_PCMCIA_PC0DRVEN 0x0010
#define BCSR_PCMCIA_PC0RST 0x0080
#define BCSR_PCMCIA_PC1VPP 0x0300
#define BCSR_PCMCIA_PC1VCC 0x0C00
#define BCSR_PCMCIA_PC1DRVEN 0x1000
#define BCSR_PCMCIA_PC1RST 0x8000
#define BCSR_BOARD_LCDVEE 0x0001
#define BCSR_BOARD_LCDVDD 0x0002
#define BCSR_BOARD_LCDBL 0x0004
#define BCSR_BOARD_CAMSNAP 0x0010
#define BCSR_BOARD_CAMPWR 0x0020
#define BCSR_BOARD_SD0PWR 0x0040
#define BCSR_LEDS_DECIMALS 0x0003
#define BCSR_LEDS_LED0 0x0100
#define BCSR_LEDS_LED1 0x0200
#define BCSR_LEDS_LED2 0x0400
#define BCSR_LEDS_LED3 0x0800
#define BCSR_SYSTEM_POWEROFF 0x4000
#define BCSR_SYSTEM_RESET 0x8000
/* Bit positions for the different interrupt sources */
#define BCSR_INT_IDE 0x0001
#define BCSR_INT_ETH 0x0002
@@ -222,7 +115,7 @@ enum external_pb1200_ints {
#define BOARD_PC0_INT DB1200_PC0_INT
#define BOARD_PC1_INT DB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET))))
/* NAND chip select */
#define NAND_CS 1