Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch
However there are similar things in the EBIU_DDRQUE Register Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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Bryan Wu
parent
9401e618c8
commit
9be343c5bc
@@ -729,6 +729,7 @@ config C_AMCKEN
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config C_CDPRIO
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config C_CDPRIO
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bool "DMA has priority over core for ext. accesses"
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bool "DMA has priority over core for ext. accesses"
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depends on !BF54x
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default n
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default n
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config C_B0PEN
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config C_B0PEN
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@@ -32,16 +32,6 @@
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#define SUPPORTED_REVID 0
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#define SUPPORTED_REVID 0
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/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
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#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
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#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
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#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
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#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
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#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
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#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \
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RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
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#define OFFSET_(x) ((x) & 0x0000FFFF)
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#define OFFSET_(x) ((x) & 0x0000FFFF)
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/*some misc defines*/
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/*some misc defines*/
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@@ -113,13 +103,8 @@
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#else
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#else
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#define V_AMCKEN 0x0
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#define V_AMCKEN 0x0
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#endif
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#endif
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#ifdef CONFIG_C_CDPRIO
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#define V_CDPRIO 0x100
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#else
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#define V_CDPRIO 0x0
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#endif
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#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
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#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
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#define MAX_VC 650000000
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#define MAX_VC 650000000
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#define MIN_VC 50000000
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#define MIN_VC 50000000
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