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bnx2x: Fix waiting for reset complete on BCM848x3 PHYs

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BCM848x3 requires additional of 50ms after reset done indication,
instead of fixed time of 200ms

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yaniv Rosner
2010-11-01 05:32:27 +00:00
committed by David S. Miller
parent 1d9c05d4d2
commit 9bffeac1ea
1 changed files with 5 additions and 3 deletions
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8
drivers/net/bnx2x/bnx2x_link.c
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@@ -5302,7 +5302,7 @@ static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
{ {
struct bnx2x *bp = params->bp; struct bnx2x *bp = params->bp;
u16 autoneg_val, an_1000_val, an_10_100_val; u16 autoneg_val, an_1000_val, an_10_100_val;
bnx2x_wait_reset_complete(bp, phy);
bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
1 << NIG_LATCH_BC_ENABLE_MI_INT); 1 << NIG_LATCH_BC_ENABLE_MI_INT);
@@ -5431,6 +5431,7 @@ static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
/* HW reset */ /* HW reset */
bnx2x_ext_phy_hw_reset(bp, params->port); bnx2x_ext_phy_hw_reset(bp, params->port);
bnx2x_wait_reset_complete(bp, phy);
bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
return bnx2x_848xx_cmn_config_init(phy, params, vars); return bnx2x_848xx_cmn_config_init(phy, params, vars);
@@ -5453,8 +5454,9 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
MISC_REGISTERS_GPIO_OUTPUT_HIGH, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
port); port);
msleep(200); /* 100 is not enough */ bnx2x_wait_reset_complete(bp, phy);
/* Wait for GPHY to come out of reset */
msleep(50);
/* BCM84823 requires that XGXS links up first @ 10G for normal /* BCM84823 requires that XGXS links up first @ 10G for normal
behavior */ behavior */
temp = vars->line_speed; temp = vars->line_speed;