iwlwifi: reorganize flow handler bitology
This patch cleans up FH bits and adds missing register values that will be used later in TX initialization rewrite Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
committed by
John W. Linville
parent
c7ab5ef9bc
commit
9c80c50211
@@ -535,7 +535,7 @@ static int iwl5000_load_section(struct iwl_priv *priv,
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iwl_write_direct32(priv,
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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iwl_release_nic_access(priv);
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iwl_release_nic_access(priv);
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@@ -549,8 +549,7 @@ static int iwl5000_load_given_ucode(struct iwl_priv *priv,
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{
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{
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int ret = 0;
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int ret = 0;
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ret = iwl5000_load_section(
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ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
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priv, inst_image, RTC_INST_LOWER_BOUND);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@@ -753,6 +752,7 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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/* map qos queues to fifos one-to-one */
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/* map qos queues to fifos one-to-one */
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for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
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for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
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int ac = iwl5000_default_queue_to_tx_fifo[i];
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int ac = iwl5000_default_queue_to_tx_fifo[i];
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@@ -318,34 +318,40 @@
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#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
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#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
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/* Find Control/Status reg for given Tx DMA/FIFO channel */
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/* Find Control/Status reg for given Tx DMA/FIFO channel */
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#define FH49_TCSR_CHNL_NUM (7)
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#define FH50_TCSR_CHNL_NUM (8)
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#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
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#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
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(FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
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(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
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#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
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(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
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(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
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#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define FH_TCSR_CHNL_NUM (7)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
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#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
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(FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
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#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
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(FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4)
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#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
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(FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8)
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/**
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/**
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* Tx Shared Status Registers (TSSR)
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* Tx Shared Status Registers (TSSR)
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@@ -432,7 +432,7 @@ static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
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/* Enable DMA channel, using same id as for TFD queue */
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/* Enable DMA channel, using same id as for TFD queue */
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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iwl_release_nic_access(priv);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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