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[ARM] MXC: remove dependency to other include files from irqs.h

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This patch removes the inclusion of mach/hardware.h from mach/irqs.h and
switches to more meaningful names for the irq related macros.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
2008-12-18 11:08:55 +01:00
parent 7c99502383
commit 9d631b835f
14 changed files with 51 additions and 53 deletions
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8
arch/arm/mach-mx1/devices.c
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@@ -232,25 +232,25 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
.chip.label = "gpio-0", .chip.label = "gpio-0",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
.irq = GPIO_INT_PORTA, .irq = GPIO_INT_PORTA,
.virtual_irq_start = MXC_MAX_INT_LINES .virtual_irq_start = MXC_GPIO_IRQ_START
}, },
[1] = { [1] = {
.chip.label = "gpio-1", .chip.label = "gpio-1",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
.irq = GPIO_INT_PORTB, .irq = GPIO_INT_PORTB,
.virtual_irq_start = MXC_MAX_INT_LINES + 32 .virtual_irq_start = MXC_GPIO_IRQ_START + 32
}, },
[2] = { [2] = {
.chip.label = "gpio-2", .chip.label = "gpio-2",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
.irq = GPIO_INT_PORTC, .irq = GPIO_INT_PORTC,
.virtual_irq_start = MXC_MAX_INT_LINES + 64 .virtual_irq_start = MXC_GPIO_IRQ_START + 64
}, },
[3] = { [3] = {
.chip.label = "gpio-3", .chip.label = "gpio-3",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
.irq = GPIO_INT_PORTD, .irq = GPIO_INT_PORTD,
.virtual_irq_start = MXC_MAX_INT_LINES + 96 .virtual_irq_start = MXC_GPIO_IRQ_START + 96
} }
}; };

12
arch/arm/mach-mx2/devices.c
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@@ -230,32 +230,32 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
.chip.label = "gpio-0", .chip.label = "gpio-0",
.irq = MXC_INT_GPIO, .irq = MXC_INT_GPIO,
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0), .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
.virtual_irq_start = MXC_MAX_INT_LINES, .virtual_irq_start = MXC_GPIO_IRQ_START,
}, },
[1] = { [1] = {
.chip.label = "gpio-1", .chip.label = "gpio-1",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1), .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
.virtual_irq_start = MXC_MAX_INT_LINES + 32, .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, },
[2] = { [2] = {
.chip.label = "gpio-2", .chip.label = "gpio-2",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2), .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
.virtual_irq_start = MXC_MAX_INT_LINES + 64, .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, },
[3] = { [3] = {
.chip.label = "gpio-3", .chip.label = "gpio-3",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3), .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
.virtual_irq_start = MXC_MAX_INT_LINES + 96, .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}, },
[4] = { [4] = {
.chip.label = "gpio-4", .chip.label = "gpio-4",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4), .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
.virtual_irq_start = MXC_MAX_INT_LINES + 128, .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
}, },
[5] = { [5] = {
.chip.label = "gpio-5", .chip.label = "gpio-5",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5), .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
.virtual_irq_start = MXC_MAX_INT_LINES + 160, .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
} }
}; };

6
arch/arm/mach-mx3/devices.c
View File

@@ -125,19 +125,19 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
.chip.label = "gpio-0", .chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR), .base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1, .irq = MXC_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_INT_BASE .virtual_irq_start = MXC_GPIO_IRQ_START,
}, },
[1] = { [1] = {
.chip.label = "gpio-1", .chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR), .base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2, .irq = MXC_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, },
[2] = { [2] = {
.chip.label = "gpio-2", .chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR), .base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3, .irq = MXC_INT_GPIO3,
.virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
} }
}; };

2
arch/arm/plat-mxc/include/mach/board-mx27ads.h
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@@ -15,7 +15,7 @@
#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ #define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
/* external interrupt multiplexer */ /* external interrupt multiplexer */
#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES) #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) #define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE #define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE

2
arch/arm/plat-mxc/include/mach/board-mx31ads.h
View File

@@ -90,7 +90,7 @@
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
#define MXC_EXP_IO_BASE (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES) #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)

4
arch/arm/plat-mxc/include/mach/gpio.h
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@@ -27,8 +27,8 @@
#define gpio_set_value __gpio_set_value #define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep #define gpio_cansleep __gpio_cansleep
#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio)) #define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio))
#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES) #define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
struct mxc_gpio_port { struct mxc_gpio_port {
void __iomem *base; void __iomem *base;

4
arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
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@@ -405,9 +405,9 @@ extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
#endif #endif
/* decode irq number to use with IMR(x), ISR(x) and friends */ /* decode irq number to use with IMR(x), ISR(x) and friends */
#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5) #define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x) #define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)

2
arch/arm/plat-mxc/include/mach/iomux-mx3.h
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@@ -141,7 +141,7 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
#define IOMUX_TO_IRQ(iomux_pin) \ #define IOMUX_TO_IRQ(iomux_pin) \
(((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
MXC_GPIO_INT_BASE) MXC_GPIO_IRQ_START)
/* /*
* This enumeration is constructed based on the Section * This enumeration is constructed based on the Section

27
arch/arm/plat-mxc/include/mach/irqs.h
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@@ -11,7 +11,32 @@
#ifndef __ASM_ARCH_MXC_IRQS_H__ #ifndef __ASM_ARCH_MXC_IRQS_H__
#define __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__
#include <mach/hardware.h> /*
* So far all i.MX SoCs have 64 internal interrupts
*/
#define MXC_INTERNAL_IRQS 64
#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
#if defined CONFIG_ARCH_MX1
#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MX2
#define MXC_GPIO_IRQS (32 * 6)
#elif defined CONFIG_ARCH_MX3
#define MXC_GPIO_IRQS (32 * 3)
#endif
/*
* The next 16 interrupts are for board specific purposes. Since
* the kernel can only run on one machine at a time, we can re-use
* these. If you need more, increase MXC_BOARD_IRQS, but keep it
* within sensible limits.
*/
#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
#define MXC_BOARD_IRQS 16
#define NR_IRQS (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
extern void imx_irq_set_priority(unsigned char irq, unsigned char prio); extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */ /* all normal IRQs can be FIQs */

4
arch/arm/plat-mxc/include/mach/mx1.h
View File

@@ -145,10 +145,6 @@
#define GPIO_INT_PORTD 62 #define GPIO_INT_PORTD 62
#define WDT_INT 63 #define WDT_INT 63
#define MXC_MAX_INT_LINES 64
#define NR_IRQS 256
/* gpio and gpio based interrupt handling */ /* gpio and gpio based interrupt handling */
#define GPIO_DR 0x1C #define GPIO_DR 0x1C
#define GPIO_GDIR 0x00 #define GPIO_GDIR 0x00

6
arch/arm/plat-mxc/include/mach/mx27.h
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@@ -295,10 +295,4 @@ extern int mx27_revision(void);
/* Start of RAM */ /* Start of RAM */
#define PHYS_OFFSET SDRAM_BASE_ADDR #define PHYS_OFFSET SDRAM_BASE_ADDR
/* max interrupt lines count */
#define NR_IRQS 256
/* count of internal interrupt sources */
#define MXC_MAX_INT_LINES 64
#endif /* __ASM_ARCH_MXC_MX27_H__ */ #endif /* __ASM_ARCH_MXC_MX27_H__ */

17
arch/arm/plat-mxc/include/mach/mx31.h
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@@ -315,23 +315,6 @@
#define MXC_INT_EXT_WDOG 62 #define MXC_INT_EXT_WDOG 62
#define MXC_INT_EXT_TV 63 #define MXC_INT_EXT_TV 63
#define MXC_MAX_INT_LINES 64
#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
#define MXC_MAX_VIRTUAL_INTS 16
#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
/*!
* Number of GPIO port as defined in the IC Spec
*/
#define GPIO_PORT_NUM 3
/*!
* Number of GPIO pins per port
*/
#define GPIO_NUM_PIN 32
#define PROD_SIGNATURE 0x1 /* For MX31 */ #define PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */ /* silicon revisions specific to i.MX31 */

8
arch/arm/plat-mxc/irq.c
View File

@@ -72,14 +72,14 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{ {
unsigned int irqt; unsigned int irqt;
if (irq >= MXC_MAX_INT_LINES) if (irq >= MXC_INTERNAL_IRQS)
return -EINVAL; return -EINVAL;
if (irq < MXC_MAX_INT_LINES / 2) { if (irq < MXC_INTERNAL_IRQS / 2) {
irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq); irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL); __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
} else { } else {
irq -= MXC_MAX_INT_LINES / 2; irq -= MXC_INTERNAL_IRQS / 2;
irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq); irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH); __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
} }
@@ -129,7 +129,7 @@ void __init mxc_init_irq(void)
/* all IRQ no FIQ */ /* all IRQ no FIQ */
__raw_writel(0, AVIC_INTTYPEH); __raw_writel(0, AVIC_INTTYPEH);
__raw_writel(0, AVIC_INTTYPEL); __raw_writel(0, AVIC_INTTYPEL);
for (i = 0; i < MXC_MAX_INT_LINES; i++) { for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxc_avic_chip); set_irq_chip(i, &mxc_avic_chip);
set_irq_handler(i, handle_level_irq); set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);

2
drivers/serial/imx.c
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@@ -191,7 +191,7 @@
#define SERIAL_IMX_MAJOR 207 #define SERIAL_IMX_MAJOR 207
#define MINOR_START 16 #define MINOR_START 16
#define DEV_NAME "ttymxc" #define DEV_NAME "ttymxc"
#define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
#endif #endif
/* /*