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arch/x86/kernel/cpu/mcheck/p4.c: cleanups

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SMP, the machine check exception dispatches all logical processors within a
physical package to the machine-check exception handler, so the printk
within each handler outputs concurrently and makes the output unreadable.
Refer to Intel system programming guide Part 1 Section 7.8.5
http://developer.intel.com/design/processor/manuals/253668.pdf

Signed-off-by: Min Zhang <mzhang@mvista.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Min Zhang
2008-01-30 13:32:11 +01:00
committed by Ingo Molnar
parent 8b2cb7a8f5
commit 9e8b6d90ac
3 changed files with 26 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/x86/kernel/cpu/mcheck/k7.c
View File

@@ -33,21 +33,24 @@ static void k7_machine_check(struct pt_regs * regs, long error_code)
for (i=1; i<nr_mce_banks; i++) { for (i=1; i<nr_mce_banks; i++) {
rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high); rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
if (high&(1<<31)) { if (high&(1<<31)) {
char misc[20];
char addr[24];
misc[0] = addr[0] = '\0';
if (high & (1<<29)) if (high & (1<<29))
recover |= 1; recover |= 1;
if (high & (1<<25)) if (high & (1<<25))
recover |= 2; recover |= 2;
printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
high &= ~(1<<31); high &= ~(1<<31);
if (high & (1<<27)) { if (high & (1<<27)) {
rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh); rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
printk ("[%08x%08x]", ahigh, alow); snprintf (misc, 20, "[%08x%08x]", ahigh, alow);
} }
if (high & (1<<26)) { if (high & (1<<26)) {
rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh); rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
printk (" at %08x%08x", ahigh, alow); snprintf (addr, 24, " at %08x%08x", ahigh, alow);
} }
printk ("\n"); printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
smp_processor_id(), i, high, low, misc, addr);
/* Clear it */ /* Clear it */
wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL); wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
/* Serialize */ /* Serialize */

21
arch/x86/kernel/cpu/mcheck/p4.c
View File

@@ -158,32 +158,35 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
if (mce_num_extended_msrs > 0) { if (mce_num_extended_msrs > 0) {
struct intel_mce_extended_msrs dbg; struct intel_mce_extended_msrs dbg;
intel_get_extended_msrs(&dbg); intel_get_extended_msrs(&dbg);
printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n", printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n"
smp_processor_id(), dbg.eip, dbg.eflags); "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n"
printk (KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n", "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
dbg.eax, dbg.ebx, dbg.ecx, dbg.edx); smp_processor_id(), dbg.eip, dbg.eflags,
printk (KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n", dbg.eax, dbg.ebx, dbg.ecx, dbg.edx,
dbg.esi, dbg.edi, dbg.ebp, dbg.esp); dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
} }
for (i=0; i<nr_mce_banks; i++) { for (i=0; i<nr_mce_banks; i++) {
rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high); rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
if (high & (1<<31)) { if (high & (1<<31)) {
char misc[20];
char addr[24];
misc[0] = addr[0] = '\0';
if (high & (1<<29)) if (high & (1<<29))
recover |= 1; recover |= 1;
if (high & (1<<25)) if (high & (1<<25))
recover |= 2; recover |= 2;
printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
high &= ~(1<<31); high &= ~(1<<31);
if (high & (1<<27)) { if (high & (1<<27)) {
rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh); rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
printk ("[%08x%08x]", ahigh, alow); snprintf (misc, 20, "[%08x%08x]", ahigh, alow);
} }
if (high & (1<<26)) { if (high & (1<<26)) {
rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh); rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
printk (" at %08x%08x", ahigh, alow); snprintf (addr, 24, " at %08x%08x", ahigh, alow);
} }
printk ("\n"); printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
smp_processor_id(), i, high, low, misc, addr);
} }
} }

11
arch/x86/kernel/cpu/mcheck/p6.c
View File

@@ -33,21 +33,24 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
for (i=0; i<nr_mce_banks; i++) { for (i=0; i<nr_mce_banks; i++) {
rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high); rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
if (high & (1<<31)) { if (high & (1<<31)) {
char misc[20];
char addr[24];
misc[0] = addr[0] = '\0';
if (high & (1<<29)) if (high & (1<<29))
recover |= 1; recover |= 1;
if (high & (1<<25)) if (high & (1<<25))
recover |= 2; recover |= 2;
printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
high &= ~(1<<31); high &= ~(1<<31);
if (high & (1<<27)) { if (high & (1<<27)) {
rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh); rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
printk ("[%08x%08x]", ahigh, alow); snprintf (misc, 20, "[%08x%08x]", ahigh, alow);
} }
if (high & (1<<26)) { if (high & (1<<26)) {
rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh); rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
printk (" at %08x%08x", ahigh, alow); snprintf (addr, 24, " at %08x%08x", ahigh, alow);
} }
printk ("\n"); printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
smp_processor_id(), i, high, low, misc, addr);
} }
} }