generic GPIO support for the Freescale Coldfire 5249.
Add support for the 5249. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Greg Ungerer
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@ -73,14 +73,14 @@
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/*
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* General purpose IO registers (in MBAR2).
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*/
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#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */
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#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */
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#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */
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#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */
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#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */
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#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */
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#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */
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#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */
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#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
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#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
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#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
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#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
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#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
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#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
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#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
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#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
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#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
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#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
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@ -100,7 +100,12 @@
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#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
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#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 64
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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/*
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* Macro to set IMR register. It is 32 bits on the 5249.
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*/
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