generic GPIO support for the Freescale Coldfire 5249.

Add support for the 5249.

Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
sfking@fdwdc.com
2009-06-19 18:11:05 -07:00
committed by Greg Ungerer
parent a03ce7d9ef
commit 9e8ded166d
3 changed files with 80 additions and 10 deletions

View File

@ -73,14 +73,14 @@
/*
* General purpose IO registers (in MBAR2).
*/
#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */
#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */
#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */
#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */
#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */
#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */
#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */
#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
@ -100,7 +100,12 @@
#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 64
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/*
* Macro to set IMR register. It is 32 bits on the 5249.
*/