Merge branch 'for-next' of git://git.infradead.org/users/sameo/mfd-2.6
* 'for-next' of git://git.infradead.org/users/sameo/mfd-2.6: (80 commits) mfd: Fix missing abx500 header file updates mfd: Add missing <linux/io.h> include to intel_msic x86, mrst: add platform support for MSIC MFD driver mfd: Expose TurnOnStatus in ab8500 sysfs mfd: Remove support for early drop ab8500 chip mfd: Add support for ab8500 v3.3 mfd: Add ab8500 interrupt disable hook mfd: Convert db8500-prcmu panic() into pr_crit() mfd: Refactor db8500-prcmu request_clock() function mfd: Rename db8500-prcmu init function mfd: Fix db5500-prcmu defines mfd: db8500-prcmu voltage domain consumers additions mfd: db8500-prcmu reset code retrieval mfd: db8500-prcmu tweak for modem wakeup mfd: Add db8500-pcmu watchdog accessor functions for watchdog mfd: hwacc power state db8500-prcmu accessor mfd: Add db8500-prcmu accessors for PLL and SGA clock mfd: Move to the new db500 PRCMU API mfd: Create a common interface for dbx500 PRCMU drivers mfd: Initialize DB8500 PRCMU regs ... Fix up trivial conflicts in arch/arm/mach-imx/mach-mx31moboard.c arch/arm/mach-omap2/board-omap3beagle.c arch/arm/mach-u300/include/mach/irqs.h drivers/mfd/wm831x-spi.c
This commit is contained in:
Linus Torvalds
140
include/linux/mfd/ab5500/ab5500.h
Normal file
140
include/linux/mfd/ab5500/ab5500.h
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@@ -0,0 +1,140 @@
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/*
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* Copyright (C) ST-Ericsson 2011
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*
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* License Terms: GNU General Public License v2
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*/
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#ifndef MFD_AB5500_H
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#define MFD_AB5500_H
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#include <linux/device.h>
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enum ab5500_devid {
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AB5500_DEVID_ADC,
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AB5500_DEVID_LEDS,
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AB5500_DEVID_POWER,
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AB5500_DEVID_REGULATORS,
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AB5500_DEVID_SIM,
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AB5500_DEVID_RTC,
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AB5500_DEVID_CHARGER,
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AB5500_DEVID_FUELGAUGE,
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AB5500_DEVID_VIBRATOR,
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AB5500_DEVID_CODEC,
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AB5500_DEVID_USB,
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AB5500_DEVID_OTP,
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AB5500_DEVID_VIDEO,
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AB5500_DEVID_DBIECI,
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AB5500_DEVID_ONSWA,
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AB5500_NUM_DEVICES,
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};
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enum ab5500_banks {
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AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
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AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
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AB5500_BANK_VDENC = 2,
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AB5500_BANK_SIM_USBSIM = 3,
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AB5500_BANK_LED = 4,
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AB5500_BANK_ADC = 5,
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AB5500_BANK_RTC = 6,
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AB5500_BANK_STARTUP = 7,
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AB5500_BANK_DBI_ECI = 8,
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AB5500_BANK_CHG = 9,
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AB5500_BANK_FG_BATTCOM_ACC = 10,
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AB5500_BANK_USB = 11,
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AB5500_BANK_IT = 12,
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AB5500_BANK_VIBRA = 13,
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AB5500_BANK_AUDIO_HEADSETUSB = 14,
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AB5500_NUM_BANKS = 15,
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};
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enum ab5500_banks_addr {
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AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
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AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
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AB5500_ADDR_VDENC = 0x06,
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AB5500_ADDR_SIM_USBSIM = 0x04,
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AB5500_ADDR_LED = 0x10,
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AB5500_ADDR_ADC = 0x0A,
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AB5500_ADDR_RTC = 0x0F,
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AB5500_ADDR_STARTUP = 0x03,
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AB5500_ADDR_DBI_ECI = 0x07,
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AB5500_ADDR_CHG = 0x0B,
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AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
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AB5500_ADDR_USB = 0x05,
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AB5500_ADDR_IT = 0x0E,
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AB5500_ADDR_VIBRA = 0x02,
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AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
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};
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/*
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* Interrupt register offsets
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* Bank : 0x0E
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*/
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#define AB5500_IT_SOURCE0_REG 0x20
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#define AB5500_IT_SOURCE1_REG 0x21
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#define AB5500_IT_SOURCE2_REG 0x22
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#define AB5500_IT_SOURCE3_REG 0x23
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#define AB5500_IT_SOURCE4_REG 0x24
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#define AB5500_IT_SOURCE5_REG 0x25
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#define AB5500_IT_SOURCE6_REG 0x26
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#define AB5500_IT_SOURCE7_REG 0x27
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#define AB5500_IT_SOURCE8_REG 0x28
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#define AB5500_IT_SOURCE9_REG 0x29
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#define AB5500_IT_SOURCE10_REG 0x2A
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#define AB5500_IT_SOURCE11_REG 0x2B
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#define AB5500_IT_SOURCE12_REG 0x2C
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#define AB5500_IT_SOURCE13_REG 0x2D
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#define AB5500_IT_SOURCE14_REG 0x2E
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#define AB5500_IT_SOURCE15_REG 0x2F
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#define AB5500_IT_SOURCE16_REG 0x30
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#define AB5500_IT_SOURCE17_REG 0x31
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#define AB5500_IT_SOURCE18_REG 0x32
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#define AB5500_IT_SOURCE19_REG 0x33
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#define AB5500_IT_SOURCE20_REG 0x34
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#define AB5500_IT_SOURCE21_REG 0x35
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#define AB5500_IT_SOURCE22_REG 0x36
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#define AB5500_IT_SOURCE23_REG 0x37
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#define AB5500_NUM_IRQ_REGS 23
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/**
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* struct ab5500
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* @access_mutex: lock out concurrent accesses to the AB registers
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* @dev: a pointer to the device struct for this chip driver
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* @ab5500_irq: the analog baseband irq
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* @irq_base: the platform configuration irq base for subdevices
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* @chip_name: name of this chip variant
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* @chip_id: 8 bit chip ID for this chip variant
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* @irq_lock: a lock to protect the mask
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* @abb_events: a local bit mask of the prcmu wakeup events
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* @event_mask: a local copy of the mask event registers
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* @last_event_mask: a copy of the last event_mask written to hardware
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* @startup_events: a copy of the first reading of the event registers
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* @startup_events_read: whether the first events have been read
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*/
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struct ab5500 {
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struct mutex access_mutex;
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struct device *dev;
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unsigned int ab5500_irq;
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unsigned int irq_base;
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char chip_name[32];
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u8 chip_id;
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struct mutex irq_lock;
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u32 abb_events;
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u8 mask[AB5500_NUM_IRQ_REGS];
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u8 oldmask[AB5500_NUM_IRQ_REGS];
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u8 startup_events[AB5500_NUM_IRQ_REGS];
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bool startup_events_read;
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#ifdef CONFIG_DEBUG_FS
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unsigned int debug_bank;
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unsigned int debug_address;
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#endif
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};
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struct ab5500_platform_data {
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struct {unsigned int base; unsigned int count; } irq;
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void *dev_data[AB5500_NUM_DEVICES];
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struct abx500_init_settings *init_settings;
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unsigned int init_settings_sz;
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bool pm_power_off;
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};
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#endif /* MFD_AB5500_H */
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@@ -27,6 +27,9 @@
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struct ab8500_gpadc;
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struct ab8500_gpadc *ab8500_gpadc_get(char *name);
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int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 input);
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int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel);
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int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel);
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int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
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u8 channel, int ad_value);
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#endif /* _AB8500_GPADC_H */
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@@ -6,7 +6,7 @@
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*
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* ABX500 core access functions.
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* The abx500 interface is used for the Analog Baseband chip
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* ab3100, ab3550, ab5500, and ab8500.
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* ab3100, ab5500, and ab8500.
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*
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* Author: Mattias Wallin <mattias.wallin@stericsson.com>
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* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
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@@ -29,17 +29,16 @@
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#define AB3100_P1G 0xc6
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#define AB3100_R2A 0xc7
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#define AB3100_R2B 0xc8
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#define AB3550_P1A 0x10
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#define AB5500_1_0 0x20
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#define AB5500_2_0 0x21
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#define AB5500_2_1 0x22
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#define AB5500_1_1 0x21
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#define AB5500_2_0 0x24
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/* AB8500 CIDs*/
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#define AB8500_CUTEARLY 0x00
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#define AB8500_CUT1P0 0x10
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#define AB8500_CUT1P1 0x11
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#define AB8500_CUT2P0 0x20
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#define AB8500_CUT3P0 0x30
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#define AB8500_CUT3P3 0x33
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/*
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* AB3100, EVENTA1, A2 and A3 event register flags
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@@ -143,39 +142,6 @@ int ab3100_event_register(struct ab3100 *ab3100,
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int ab3100_event_unregister(struct ab3100 *ab3100,
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struct notifier_block *nb);
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/* AB3550, STR register flags */
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#define AB3550_STR_ONSWA (0x01)
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#define AB3550_STR_ONSWB (0x02)
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#define AB3550_STR_ONSWC (0x04)
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#define AB3550_STR_DCIO (0x08)
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#define AB3550_STR_BOOT_MODE (0x10)
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#define AB3550_STR_SIM_OFF (0x20)
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#define AB3550_STR_BATT_REMOVAL (0x40)
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#define AB3550_STR_VBUS (0x80)
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/* Interrupt mask registers */
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#define AB3550_IMR1 0x29
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#define AB3550_IMR2 0x2a
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#define AB3550_IMR3 0x2b
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#define AB3550_IMR4 0x2c
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#define AB3550_IMR5 0x2d
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enum ab3550_devid {
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AB3550_DEVID_ADC,
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AB3550_DEVID_DAC,
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AB3550_DEVID_LEDS,
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AB3550_DEVID_POWER,
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AB3550_DEVID_REGULATORS,
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AB3550_DEVID_SIM,
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AB3550_DEVID_UART,
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AB3550_DEVID_RTC,
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AB3550_DEVID_CHARGER,
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AB3550_DEVID_FUELGAUGE,
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AB3550_DEVID_VIBRATOR,
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AB3550_DEVID_CODEC,
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AB3550_NUM_DEVICES,
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};
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/**
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* struct abx500_init_setting
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* Initial value of the registers for driver to use during setup.
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@@ -186,18 +152,6 @@ struct abx500_init_settings {
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u8 setting;
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};
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/**
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* struct ab3550_platform_data
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* Data supplied to initialize board connections to the AB3550
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*/
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struct ab3550_platform_data {
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struct {unsigned int base; unsigned int count; } irq;
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void *dev_data[AB3550_NUM_DEVICES];
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size_t dev_data_sz[AB3550_NUM_DEVICES];
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struct abx500_init_settings *init_settings;
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unsigned int init_settings_sz;
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};
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int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
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u8 value);
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int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
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@@ -5,21 +5,35 @@
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*
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* U5500 PRCMU API.
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*/
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#ifndef __MACH_PRCMU_U5500_H
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#define __MACH_PRCMU_U5500_H
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#ifndef __MFD_DB5500_PRCMU_H
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#define __MFD_DB5500_PRCMU_H
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#ifdef CONFIG_UX500_SOC_DB5500
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#ifdef CONFIG_MFD_DB5500_PRCMU
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void db5500_prcmu_early_init(void);
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int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state);
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int db5500_prcmu_set_display_clocks(void);
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int db5500_prcmu_disable_dsipll(void);
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int db5500_prcmu_enable_dsipll(void);
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int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
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int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
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void db5500_prcmu_enable_wakeups(u32 wakeups);
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int db5500_prcmu_request_clock(u8 clock, bool enable);
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void db5500_prcmu_config_abb_event_readout(u32 abb_events);
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void db5500_prcmu_get_abb_event_buffer(void __iomem **buf);
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int prcmu_resetout(u8 resoutn, u8 state);
|
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int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
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bool keep_ap_pll);
|
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int db5500_prcmu_config_esram0_deep_sleep(u8 state);
|
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void db5500_prcmu_system_reset(u16 reset_code);
|
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u16 db5500_prcmu_get_reset_code(void);
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bool db5500_prcmu_is_ac_wake_requested(void);
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int db5500_prcmu_set_arm_opp(u8 opp);
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int db5500_prcmu_get_arm_opp(void);
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|
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#else /* !CONFIG_UX500_SOC_DB5500 */
|
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|
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static inline void db5500_prcmu_early_init(void)
|
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{
|
||||
}
|
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static inline void db5500_prcmu_early_init(void) {}
|
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|
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static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
|
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{
|
||||
@@ -31,15 +45,75 @@ static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
|
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return -ENOSYS;
|
||||
}
|
||||
|
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#endif /* CONFIG_UX500_SOC_DB5500 */
|
||||
|
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static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
|
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static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
#ifdef CONFIG_MACH_U5500_SIMULATOR
|
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return 0;
|
||||
#else
|
||||
return -1;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* __MACH_PRCMU_U5500_H */
|
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static inline int db5500_prcmu_set_display_clocks(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_disable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_enable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
|
||||
|
||||
static inline int prcmu_resetout(u8 resoutn, u8 state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
|
||||
static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
|
||||
|
||||
static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
||||
bool keep_ap_pll)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db5500_prcmu_system_reset(u16 reset_code) {}
|
||||
|
||||
static inline u16 db5500_prcmu_get_reset_code(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool db5500_prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_get_arm_opp(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_MFD_DB5500_PRCMU */
|
||||
|
||||
#endif /* __MFD_DB5500_PRCMU_H */
|
||||
|
||||
@@ -11,7 +11,6 @@
|
||||
#define __MFD_DB8500_PRCMU_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/notifier.h>
|
||||
|
||||
/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
|
||||
|
||||
@@ -133,7 +132,7 @@ enum ap_pwrst {
|
||||
* @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
|
||||
*/
|
||||
enum ap_pwrst_trans {
|
||||
NO_TRANSITION = 0x00,
|
||||
PRCMU_AP_NO_CHANGE = 0x00,
|
||||
APEXECUTE_TO_APSLEEP = 0x01,
|
||||
APIDLE_TO_APSLEEP = 0x02, /* To be removed */
|
||||
PRCMU_AP_SLEEP = 0x01,
|
||||
@@ -145,54 +144,6 @@ enum ap_pwrst_trans {
|
||||
PRCMU_AP_DEEP_IDLE = 0x07,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ddr_pwrst - DDR power states definition
|
||||
* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
|
||||
* @DDR_PWR_STATE_ON:
|
||||
* @DDR_PWR_STATE_OFFLOWLAT:
|
||||
* @DDR_PWR_STATE_OFFHIGHLAT:
|
||||
*/
|
||||
enum ddr_pwrst {
|
||||
DDR_PWR_STATE_UNCHANGED = 0x00,
|
||||
DDR_PWR_STATE_ON = 0x01,
|
||||
DDR_PWR_STATE_OFFLOWLAT = 0x02,
|
||||
DDR_PWR_STATE_OFFHIGHLAT = 0x03
|
||||
};
|
||||
|
||||
/**
|
||||
* enum arm_opp - ARM OPP states definition
|
||||
* @ARM_OPP_INIT:
|
||||
* @ARM_NO_CHANGE: The ARM operating point is unchanged
|
||||
* @ARM_100_OPP: The new ARM operating point is arm100opp
|
||||
* @ARM_50_OPP: The new ARM operating point is arm50opp
|
||||
* @ARM_MAX_OPP: Operating point is "max" (more than 100)
|
||||
* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
|
||||
* @ARM_EXTCLK: The new ARM operating point is armExtClk
|
||||
*/
|
||||
enum arm_opp {
|
||||
ARM_OPP_INIT = 0x00,
|
||||
ARM_NO_CHANGE = 0x01,
|
||||
ARM_100_OPP = 0x02,
|
||||
ARM_50_OPP = 0x03,
|
||||
ARM_MAX_OPP = 0x04,
|
||||
ARM_MAX_FREQ100OPP = 0x05,
|
||||
ARM_EXTCLK = 0x07
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ape_opp - APE OPP states definition
|
||||
* @APE_OPP_INIT:
|
||||
* @APE_NO_CHANGE: The APE operating point is unchanged
|
||||
* @APE_100_OPP: The new APE operating point is ape100opp
|
||||
* @APE_50_OPP: 50%
|
||||
*/
|
||||
enum ape_opp {
|
||||
APE_OPP_INIT = 0x00,
|
||||
APE_NO_CHANGE = 0x01,
|
||||
APE_100_OPP = 0x02,
|
||||
APE_50_OPP = 0x03
|
||||
};
|
||||
|
||||
/**
|
||||
* enum hw_acc_state - State definition for hardware accelerator
|
||||
* @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
|
||||
@@ -469,26 +420,6 @@ enum auto_enable {
|
||||
|
||||
/* End of file previously known as prcmu-fw-defs_v1.h */
|
||||
|
||||
/* PRCMU Wakeup defines */
|
||||
enum prcmu_wakeup_index {
|
||||
PRCMU_WAKEUP_INDEX_RTC,
|
||||
PRCMU_WAKEUP_INDEX_RTT0,
|
||||
PRCMU_WAKEUP_INDEX_RTT1,
|
||||
PRCMU_WAKEUP_INDEX_HSI0,
|
||||
PRCMU_WAKEUP_INDEX_HSI1,
|
||||
PRCMU_WAKEUP_INDEX_USB,
|
||||
PRCMU_WAKEUP_INDEX_ABB,
|
||||
PRCMU_WAKEUP_INDEX_ABB_FIFO,
|
||||
PRCMU_WAKEUP_INDEX_ARM,
|
||||
NUM_PRCMU_WAKEUP_INDICES
|
||||
};
|
||||
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
|
||||
|
||||
/* PRCMU QoS APE OPP class */
|
||||
#define PRCMU_QOS_APE_OPP 1
|
||||
#define PRCMU_QOS_DDR_OPP 2
|
||||
#define PRCMU_QOS_DEFAULT_VALUE -1
|
||||
|
||||
/**
|
||||
* enum hw_acc_dev - enum for hw accelerators
|
||||
* @HW_ACC_SVAMMDSP: for SVAMMDSP
|
||||
@@ -526,64 +457,6 @@ enum hw_acc_dev {
|
||||
NUM_HW_ACC
|
||||
};
|
||||
|
||||
/*
|
||||
* Ids for all EPODs (power domains)
|
||||
* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
|
||||
* - EPOD_ID_SVAPIPE: power domain for SVA pipe
|
||||
* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
|
||||
* - EPOD_ID_SIAPIPE: power domain for SIA pipe
|
||||
* - EPOD_ID_SGA: power domain for SGA
|
||||
* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
|
||||
* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
|
||||
* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
|
||||
* - NUM_EPOD_ID: number of power domains
|
||||
*/
|
||||
#define EPOD_ID_SVAMMDSP 0
|
||||
#define EPOD_ID_SVAPIPE 1
|
||||
#define EPOD_ID_SIAMMDSP 2
|
||||
#define EPOD_ID_SIAPIPE 3
|
||||
#define EPOD_ID_SGA 4
|
||||
#define EPOD_ID_B2R2_MCDE 5
|
||||
#define EPOD_ID_ESRAM12 6
|
||||
#define EPOD_ID_ESRAM34 7
|
||||
#define NUM_EPOD_ID 8
|
||||
|
||||
/*
|
||||
* state definition for EPOD (power domain)
|
||||
* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
|
||||
* - EPOD_STATE_OFF: The EPOD is switched off
|
||||
* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
|
||||
* retention
|
||||
* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
|
||||
* - EPOD_STATE_ON: Same as above, but with clock enabled
|
||||
*/
|
||||
#define EPOD_STATE_NO_CHANGE 0x00
|
||||
#define EPOD_STATE_OFF 0x01
|
||||
#define EPOD_STATE_RAMRET 0x02
|
||||
#define EPOD_STATE_ON_CLK_OFF 0x03
|
||||
#define EPOD_STATE_ON 0x04
|
||||
|
||||
/*
|
||||
* CLKOUT sources
|
||||
*/
|
||||
#define PRCMU_CLKSRC_CLK38M 0x00
|
||||
#define PRCMU_CLKSRC_ACLK 0x01
|
||||
#define PRCMU_CLKSRC_SYSCLK 0x02
|
||||
#define PRCMU_CLKSRC_LCDCLK 0x03
|
||||
#define PRCMU_CLKSRC_SDMMCCLK 0x04
|
||||
#define PRCMU_CLKSRC_TVCLK 0x05
|
||||
#define PRCMU_CLKSRC_TIMCLK 0x06
|
||||
#define PRCMU_CLKSRC_CLK009 0x07
|
||||
/* These are only valid for CLKOUT1: */
|
||||
#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
|
||||
#define PRCMU_CLKSRC_I2CCLK 0x41
|
||||
#define PRCMU_CLKSRC_MSP02CLK 0x42
|
||||
#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
|
||||
#define PRCMU_CLKSRC_HSIRXCLK 0x44
|
||||
#define PRCMU_CLKSRC_HSITXCLK 0x45
|
||||
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
|
||||
#define PRCMU_CLKSRC_HDMICLK 0x47
|
||||
|
||||
/*
|
||||
* Definitions for autonomous power management configuration.
|
||||
*/
|
||||
@@ -620,88 +493,12 @@ struct prcmu_auto_pm_config {
|
||||
u8 sva_policy;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ddr_opp - DDR OPP states definition
|
||||
* @DDR_100_OPP: The new DDR operating point is ddr100opp
|
||||
* @DDR_50_OPP: The new DDR operating point is ddr50opp
|
||||
* @DDR_25_OPP: The new DDR operating point is ddr25opp
|
||||
*/
|
||||
enum ddr_opp {
|
||||
DDR_100_OPP = 0x00,
|
||||
DDR_50_OPP = 0x01,
|
||||
DDR_25_OPP = 0x02,
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock identifiers.
|
||||
*/
|
||||
enum prcmu_clock {
|
||||
PRCMU_SGACLK,
|
||||
PRCMU_UARTCLK,
|
||||
PRCMU_MSP02CLK,
|
||||
PRCMU_MSP1CLK,
|
||||
PRCMU_I2CCLK,
|
||||
PRCMU_SDMMCCLK,
|
||||
PRCMU_SLIMCLK,
|
||||
PRCMU_PER1CLK,
|
||||
PRCMU_PER2CLK,
|
||||
PRCMU_PER3CLK,
|
||||
PRCMU_PER5CLK,
|
||||
PRCMU_PER6CLK,
|
||||
PRCMU_PER7CLK,
|
||||
PRCMU_LCDCLK,
|
||||
PRCMU_BMLCLK,
|
||||
PRCMU_HSITXCLK,
|
||||
PRCMU_HSIRXCLK,
|
||||
PRCMU_HDMICLK,
|
||||
PRCMU_APEATCLK,
|
||||
PRCMU_APETRACECLK,
|
||||
PRCMU_MCDECLK,
|
||||
PRCMU_IPI2CCLK,
|
||||
PRCMU_DSIALTCLK,
|
||||
PRCMU_DMACLK,
|
||||
PRCMU_B2R2CLK,
|
||||
PRCMU_TVCLK,
|
||||
PRCMU_SSPCLK,
|
||||
PRCMU_RNGCLK,
|
||||
PRCMU_UICCCLK,
|
||||
PRCMU_NUM_REG_CLOCKS,
|
||||
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
|
||||
PRCMU_TIMCLK,
|
||||
};
|
||||
|
||||
/*
|
||||
* Definitions for controlling ESRAM0 in deep sleep.
|
||||
*/
|
||||
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
|
||||
#define ESRAM0_DEEP_SLEEP_STATE_RET 2
|
||||
|
||||
#ifdef CONFIG_MFD_DB8500_PRCMU
|
||||
void __init prcmu_early_init(void);
|
||||
int prcmu_set_display_clocks(void);
|
||||
int prcmu_disable_dsipll(void);
|
||||
int prcmu_enable_dsipll(void);
|
||||
#else
|
||||
static inline void __init prcmu_early_init(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MFD_DB8500_PRCMU
|
||||
|
||||
void db8500_prcmu_early_init(void);
|
||||
int prcmu_set_rc_a2p(enum romcode_write);
|
||||
enum romcode_read prcmu_get_rc_p2a(void);
|
||||
enum ap_pwrst prcmu_get_xp70_current_state(void);
|
||||
int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
|
||||
|
||||
void prcmu_enable_wakeups(u32 wakeups);
|
||||
static inline void prcmu_disable_wakeups(void)
|
||||
{
|
||||
prcmu_enable_wakeups(0);
|
||||
}
|
||||
|
||||
void prcmu_config_abb_event_readout(u32 abb_events);
|
||||
void prcmu_get_abb_event_buffer(void __iomem **buf);
|
||||
int prcmu_set_arm_opp(u8 opp);
|
||||
int prcmu_get_arm_opp(void);
|
||||
bool prcmu_has_arm_maxopp(void);
|
||||
bool prcmu_is_u8400(void);
|
||||
int prcmu_set_ape_opp(u8 opp);
|
||||
@@ -710,19 +507,14 @@ int prcmu_request_ape_opp_100_voltage(bool enable);
|
||||
int prcmu_release_usb_wakeup_state(void);
|
||||
int prcmu_set_ddr_opp(u8 opp);
|
||||
int prcmu_get_ddr_opp(void);
|
||||
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
|
||||
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
|
||||
/* NOTE! Use regulator framework instead */
|
||||
int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
|
||||
int prcmu_set_epod(u16 epod_id, u8 epod_state);
|
||||
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
|
||||
struct prcmu_auto_pm_config *idle);
|
||||
bool prcmu_is_auto_pm_enabled(void);
|
||||
|
||||
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
|
||||
int prcmu_request_clock(u8 clock, bool enable);
|
||||
int prcmu_set_clock_divider(u8 clock, u8 divider);
|
||||
int prcmu_config_esram0_deep_sleep(u8 state);
|
||||
int prcmu_config_hotdog(u8 threshold);
|
||||
int prcmu_config_hotmon(u8 low, u8 high);
|
||||
int prcmu_start_temp_sense(u16 cycles32k);
|
||||
@@ -732,14 +524,36 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
|
||||
|
||||
void prcmu_ac_wake_req(void);
|
||||
void prcmu_ac_sleep_req(void);
|
||||
void prcmu_system_reset(u16 reset_code);
|
||||
void prcmu_modem_reset(void);
|
||||
bool prcmu_is_ac_wake_requested(void);
|
||||
void prcmu_enable_spi2(void);
|
||||
void prcmu_disable_spi2(void);
|
||||
|
||||
int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
|
||||
int prcmu_enable_a9wdog(u8 id);
|
||||
int prcmu_disable_a9wdog(u8 id);
|
||||
int prcmu_kick_a9wdog(u8 id);
|
||||
int prcmu_load_a9wdog(u8 id, u32 val);
|
||||
|
||||
void db8500_prcmu_system_reset(u16 reset_code);
|
||||
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
|
||||
void db8500_prcmu_enable_wakeups(u32 wakeups);
|
||||
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
|
||||
int db8500_prcmu_request_clock(u8 clock, bool enable);
|
||||
int db8500_prcmu_set_display_clocks(void);
|
||||
int db8500_prcmu_disable_dsipll(void);
|
||||
int db8500_prcmu_enable_dsipll(void);
|
||||
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
|
||||
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
|
||||
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
|
||||
u16 db8500_prcmu_get_reset_code(void);
|
||||
bool db8500_prcmu_is_ac_wake_requested(void);
|
||||
int db8500_prcmu_set_arm_opp(u8 opp);
|
||||
int db8500_prcmu_get_arm_opp(void);
|
||||
|
||||
#else /* !CONFIG_MFD_DB8500_PRCMU */
|
||||
|
||||
static inline void db8500_prcmu_early_init(void) {}
|
||||
|
||||
static inline int prcmu_set_rc_a2p(enum romcode_write code)
|
||||
{
|
||||
return 0;
|
||||
@@ -755,34 +569,12 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
|
||||
return AP_EXECUTE;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
||||
bool keep_ap_pll)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_enable_wakeups(u32 wakeups) {}
|
||||
|
||||
static inline void prcmu_disable_wakeups(void) {}
|
||||
|
||||
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
|
||||
|
||||
static inline int prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_get_arm_opp(void)
|
||||
{
|
||||
return ARM_100_OPP;
|
||||
}
|
||||
|
||||
static bool prcmu_has_arm_maxopp(void)
|
||||
static inline bool prcmu_has_arm_maxopp(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool prcmu_is_u8400(void)
|
||||
static inline bool prcmu_is_u8400(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
@@ -817,13 +609,6 @@ static inline int prcmu_get_ddr_opp(void)
|
||||
return DDR_100_OPP;
|
||||
}
|
||||
|
||||
static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
|
||||
|
||||
static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
|
||||
{
|
||||
return 0;
|
||||
@@ -844,21 +629,11 @@ static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_hotdog(u8 threshold)
|
||||
{
|
||||
return 0;
|
||||
@@ -893,32 +668,8 @@ static inline void prcmu_ac_wake_req(void) {}
|
||||
|
||||
static inline void prcmu_ac_sleep_req(void) {}
|
||||
|
||||
static inline void prcmu_system_reset(u16 reset_code) {}
|
||||
|
||||
static inline void prcmu_modem_reset(void) {}
|
||||
|
||||
static inline bool prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_UX500_SOC_DB5500
|
||||
static inline int prcmu_set_display_clocks(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_disable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_enable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int prcmu_enable_spi2(void)
|
||||
{
|
||||
return 0;
|
||||
@@ -929,50 +680,95 @@ static inline int prcmu_disable_spi2(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
|
||||
|
||||
static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
||||
bool keep_ap_pll)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
|
||||
|
||||
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_set_display_clocks(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_disable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_enable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
|
||||
|
||||
static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
|
||||
|
||||
static inline u16 db8500_prcmu_get_reset_code(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_enable_a9wdog(u8 id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_disable_a9wdog(u8 id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_kick_a9wdog(u8 id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_load_a9wdog(u8 id, u32 val)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool db8500_prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int db8500_prcmu_get_arm_opp(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_MFD_DB8500_PRCMU */
|
||||
|
||||
#ifdef CONFIG_UX500_PRCMU_QOS_POWER
|
||||
int prcmu_qos_requirement(int pm_qos_class);
|
||||
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
|
||||
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
|
||||
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
|
||||
int prcmu_qos_add_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier);
|
||||
int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier);
|
||||
#else
|
||||
static inline int prcmu_qos_requirement(int prcmu_qos_class)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
|
||||
char *name, s32 value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
|
||||
char *name, s32 new_value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __MFD_DB8500_PRCMU_H */
|
||||
|
||||
549
include/linux/mfd/dbx500-prcmu.h
Normal file
549
include/linux/mfd/dbx500-prcmu.h
Normal file
@@ -0,0 +1,549 @@
|
||||
/*
|
||||
* Copyright (C) ST Ericsson SA 2011
|
||||
*
|
||||
* License Terms: GNU General Public License v2
|
||||
*
|
||||
* STE Ux500 PRCMU API
|
||||
*/
|
||||
#ifndef __MACH_PRCMU_H
|
||||
#define __MACH_PRCMU_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
/* PRCMU Wakeup defines */
|
||||
enum prcmu_wakeup_index {
|
||||
PRCMU_WAKEUP_INDEX_RTC,
|
||||
PRCMU_WAKEUP_INDEX_RTT0,
|
||||
PRCMU_WAKEUP_INDEX_RTT1,
|
||||
PRCMU_WAKEUP_INDEX_HSI0,
|
||||
PRCMU_WAKEUP_INDEX_HSI1,
|
||||
PRCMU_WAKEUP_INDEX_USB,
|
||||
PRCMU_WAKEUP_INDEX_ABB,
|
||||
PRCMU_WAKEUP_INDEX_ABB_FIFO,
|
||||
PRCMU_WAKEUP_INDEX_ARM,
|
||||
PRCMU_WAKEUP_INDEX_CD_IRQ,
|
||||
NUM_PRCMU_WAKEUP_INDICES
|
||||
};
|
||||
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
|
||||
|
||||
/* EPOD (power domain) IDs */
|
||||
|
||||
/*
|
||||
* DB8500 EPODs
|
||||
* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
|
||||
* - EPOD_ID_SVAPIPE: power domain for SVA pipe
|
||||
* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
|
||||
* - EPOD_ID_SIAPIPE: power domain for SIA pipe
|
||||
* - EPOD_ID_SGA: power domain for SGA
|
||||
* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
|
||||
* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
|
||||
* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
|
||||
* - NUM_EPOD_ID: number of power domains
|
||||
*
|
||||
* TODO: These should be prefixed.
|
||||
*/
|
||||
#define EPOD_ID_SVAMMDSP 0
|
||||
#define EPOD_ID_SVAPIPE 1
|
||||
#define EPOD_ID_SIAMMDSP 2
|
||||
#define EPOD_ID_SIAPIPE 3
|
||||
#define EPOD_ID_SGA 4
|
||||
#define EPOD_ID_B2R2_MCDE 5
|
||||
#define EPOD_ID_ESRAM12 6
|
||||
#define EPOD_ID_ESRAM34 7
|
||||
#define NUM_EPOD_ID 8
|
||||
|
||||
/*
|
||||
* DB5500 EPODs
|
||||
*/
|
||||
#define DB5500_EPOD_ID_BASE 0x0100
|
||||
#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
|
||||
#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
|
||||
#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
|
||||
#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
|
||||
#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
|
||||
#define DB5500_NUM_EPOD_ID 7
|
||||
|
||||
/*
|
||||
* state definition for EPOD (power domain)
|
||||
* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
|
||||
* - EPOD_STATE_OFF: The EPOD is switched off
|
||||
* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
|
||||
* retention
|
||||
* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
|
||||
* - EPOD_STATE_ON: Same as above, but with clock enabled
|
||||
*/
|
||||
#define EPOD_STATE_NO_CHANGE 0x00
|
||||
#define EPOD_STATE_OFF 0x01
|
||||
#define EPOD_STATE_RAMRET 0x02
|
||||
#define EPOD_STATE_ON_CLK_OFF 0x03
|
||||
#define EPOD_STATE_ON 0x04
|
||||
|
||||
/*
|
||||
* CLKOUT sources
|
||||
*/
|
||||
#define PRCMU_CLKSRC_CLK38M 0x00
|
||||
#define PRCMU_CLKSRC_ACLK 0x01
|
||||
#define PRCMU_CLKSRC_SYSCLK 0x02
|
||||
#define PRCMU_CLKSRC_LCDCLK 0x03
|
||||
#define PRCMU_CLKSRC_SDMMCCLK 0x04
|
||||
#define PRCMU_CLKSRC_TVCLK 0x05
|
||||
#define PRCMU_CLKSRC_TIMCLK 0x06
|
||||
#define PRCMU_CLKSRC_CLK009 0x07
|
||||
/* These are only valid for CLKOUT1: */
|
||||
#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
|
||||
#define PRCMU_CLKSRC_I2CCLK 0x41
|
||||
#define PRCMU_CLKSRC_MSP02CLK 0x42
|
||||
#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
|
||||
#define PRCMU_CLKSRC_HSIRXCLK 0x44
|
||||
#define PRCMU_CLKSRC_HSITXCLK 0x45
|
||||
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
|
||||
#define PRCMU_CLKSRC_HDMICLK 0x47
|
||||
|
||||
/*
|
||||
* Clock identifiers.
|
||||
*/
|
||||
enum prcmu_clock {
|
||||
PRCMU_SGACLK,
|
||||
PRCMU_UARTCLK,
|
||||
PRCMU_MSP02CLK,
|
||||
PRCMU_MSP1CLK,
|
||||
PRCMU_I2CCLK,
|
||||
PRCMU_SDMMCCLK,
|
||||
PRCMU_SLIMCLK,
|
||||
PRCMU_PER1CLK,
|
||||
PRCMU_PER2CLK,
|
||||
PRCMU_PER3CLK,
|
||||
PRCMU_PER5CLK,
|
||||
PRCMU_PER6CLK,
|
||||
PRCMU_PER7CLK,
|
||||
PRCMU_LCDCLK,
|
||||
PRCMU_BMLCLK,
|
||||
PRCMU_HSITXCLK,
|
||||
PRCMU_HSIRXCLK,
|
||||
PRCMU_HDMICLK,
|
||||
PRCMU_APEATCLK,
|
||||
PRCMU_APETRACECLK,
|
||||
PRCMU_MCDECLK,
|
||||
PRCMU_IPI2CCLK,
|
||||
PRCMU_DSIALTCLK,
|
||||
PRCMU_DMACLK,
|
||||
PRCMU_B2R2CLK,
|
||||
PRCMU_TVCLK,
|
||||
PRCMU_SSPCLK,
|
||||
PRCMU_RNGCLK,
|
||||
PRCMU_UICCCLK,
|
||||
PRCMU_PWMCLK,
|
||||
PRCMU_IRDACLK,
|
||||
PRCMU_IRRCCLK,
|
||||
PRCMU_SIACLK,
|
||||
PRCMU_SVACLK,
|
||||
PRCMU_NUM_REG_CLOCKS,
|
||||
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
|
||||
PRCMU_TIMCLK,
|
||||
PRCMU_PLLSOC0,
|
||||
PRCMU_PLLSOC1,
|
||||
PRCMU_PLLDDR,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ape_opp - APE OPP states definition
|
||||
* @APE_OPP_INIT:
|
||||
* @APE_NO_CHANGE: The APE operating point is unchanged
|
||||
* @APE_100_OPP: The new APE operating point is ape100opp
|
||||
* @APE_50_OPP: 50%
|
||||
*/
|
||||
enum ape_opp {
|
||||
APE_OPP_INIT = 0x00,
|
||||
APE_NO_CHANGE = 0x01,
|
||||
APE_100_OPP = 0x02,
|
||||
APE_50_OPP = 0x03
|
||||
};
|
||||
|
||||
/**
|
||||
* enum arm_opp - ARM OPP states definition
|
||||
* @ARM_OPP_INIT:
|
||||
* @ARM_NO_CHANGE: The ARM operating point is unchanged
|
||||
* @ARM_100_OPP: The new ARM operating point is arm100opp
|
||||
* @ARM_50_OPP: The new ARM operating point is arm50opp
|
||||
* @ARM_MAX_OPP: Operating point is "max" (more than 100)
|
||||
* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
|
||||
* @ARM_EXTCLK: The new ARM operating point is armExtClk
|
||||
*/
|
||||
enum arm_opp {
|
||||
ARM_OPP_INIT = 0x00,
|
||||
ARM_NO_CHANGE = 0x01,
|
||||
ARM_100_OPP = 0x02,
|
||||
ARM_50_OPP = 0x03,
|
||||
ARM_MAX_OPP = 0x04,
|
||||
ARM_MAX_FREQ100OPP = 0x05,
|
||||
ARM_EXTCLK = 0x07
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ddr_opp - DDR OPP states definition
|
||||
* @DDR_100_OPP: The new DDR operating point is ddr100opp
|
||||
* @DDR_50_OPP: The new DDR operating point is ddr50opp
|
||||
* @DDR_25_OPP: The new DDR operating point is ddr25opp
|
||||
*/
|
||||
enum ddr_opp {
|
||||
DDR_100_OPP = 0x00,
|
||||
DDR_50_OPP = 0x01,
|
||||
DDR_25_OPP = 0x02,
|
||||
};
|
||||
|
||||
/*
|
||||
* Definitions for controlling ESRAM0 in deep sleep.
|
||||
*/
|
||||
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
|
||||
#define ESRAM0_DEEP_SLEEP_STATE_RET 2
|
||||
|
||||
/**
|
||||
* enum ddr_pwrst - DDR power states definition
|
||||
* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
|
||||
* @DDR_PWR_STATE_ON:
|
||||
* @DDR_PWR_STATE_OFFLOWLAT:
|
||||
* @DDR_PWR_STATE_OFFHIGHLAT:
|
||||
*/
|
||||
enum ddr_pwrst {
|
||||
DDR_PWR_STATE_UNCHANGED = 0x00,
|
||||
DDR_PWR_STATE_ON = 0x01,
|
||||
DDR_PWR_STATE_OFFLOWLAT = 0x02,
|
||||
DDR_PWR_STATE_OFFHIGHLAT = 0x03
|
||||
};
|
||||
|
||||
#include <linux/mfd/db8500-prcmu.h>
|
||||
#include <linux/mfd/db5500-prcmu.h>
|
||||
|
||||
#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
|
||||
|
||||
static inline void __init prcmu_early_init(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_early_init();
|
||||
else
|
||||
return db8500_prcmu_early_init();
|
||||
}
|
||||
|
||||
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
||||
bool keep_ap_pll)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_set_power_state(state, keep_ulp_clk,
|
||||
keep_ap_pll);
|
||||
else
|
||||
return db8500_prcmu_set_power_state(state, keep_ulp_clk,
|
||||
keep_ap_pll);
|
||||
}
|
||||
|
||||
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_set_epod(epod_id, epod_state);
|
||||
}
|
||||
|
||||
static inline void prcmu_enable_wakeups(u32 wakeups)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
db5500_prcmu_enable_wakeups(wakeups);
|
||||
else
|
||||
db8500_prcmu_enable_wakeups(wakeups);
|
||||
}
|
||||
|
||||
static inline void prcmu_disable_wakeups(void)
|
||||
{
|
||||
prcmu_enable_wakeups(0);
|
||||
}
|
||||
|
||||
static inline void prcmu_config_abb_event_readout(u32 abb_events)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
db5500_prcmu_config_abb_event_readout(abb_events);
|
||||
else
|
||||
db8500_prcmu_config_abb_event_readout(abb_events);
|
||||
}
|
||||
|
||||
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
db5500_prcmu_get_abb_event_buffer(buf);
|
||||
else
|
||||
db8500_prcmu_get_abb_event_buffer(buf);
|
||||
}
|
||||
|
||||
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
|
||||
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
|
||||
|
||||
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
|
||||
|
||||
static inline int prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_request_clock(clock, enable);
|
||||
else
|
||||
return db8500_prcmu_request_clock(clock, enable);
|
||||
}
|
||||
|
||||
int prcmu_set_ape_opp(u8 opp);
|
||||
int prcmu_get_ape_opp(void);
|
||||
int prcmu_set_ddr_opp(u8 opp);
|
||||
int prcmu_get_ddr_opp(void);
|
||||
|
||||
static inline int prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_set_arm_opp(opp);
|
||||
}
|
||||
|
||||
static inline int prcmu_get_arm_opp(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_get_arm_opp();
|
||||
}
|
||||
|
||||
static inline void prcmu_system_reset(u16 reset_code)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_system_reset(reset_code);
|
||||
else
|
||||
return db8500_prcmu_system_reset(reset_code);
|
||||
}
|
||||
|
||||
static inline u16 prcmu_get_reset_code(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_get_reset_code();
|
||||
else
|
||||
return db8500_prcmu_get_reset_code();
|
||||
}
|
||||
|
||||
void prcmu_ac_wake_req(void);
|
||||
void prcmu_ac_sleep_req(void);
|
||||
void prcmu_modem_reset(void);
|
||||
static inline bool prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_is_ac_wake_requested();
|
||||
else
|
||||
return db8500_prcmu_is_ac_wake_requested();
|
||||
}
|
||||
|
||||
static inline int prcmu_set_display_clocks(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_set_display_clocks();
|
||||
else
|
||||
return db8500_prcmu_set_display_clocks();
|
||||
}
|
||||
|
||||
static inline int prcmu_disable_dsipll(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_disable_dsipll();
|
||||
else
|
||||
return db8500_prcmu_disable_dsipll();
|
||||
}
|
||||
|
||||
static inline int prcmu_enable_dsipll(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return db5500_prcmu_enable_dsipll();
|
||||
else
|
||||
return db8500_prcmu_enable_dsipll();
|
||||
}
|
||||
|
||||
static inline int prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_config_esram0_deep_sleep(state);
|
||||
}
|
||||
#else
|
||||
|
||||
static inline void __init prcmu_early_init(void) {}
|
||||
|
||||
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
||||
bool keep_ap_pll)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_enable_wakeups(u32 wakeups) {}
|
||||
|
||||
static inline void prcmu_disable_wakeups(void) {}
|
||||
|
||||
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_ape_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_get_ape_opp(void)
|
||||
{
|
||||
return APE_100_OPP;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_get_arm_opp(void)
|
||||
{
|
||||
return ARM_100_OPP;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_ddr_opp(u8 opp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_get_ddr_opp(void)
|
||||
{
|
||||
return DDR_100_OPP;
|
||||
}
|
||||
|
||||
static inline void prcmu_system_reset(u16 reset_code) {}
|
||||
|
||||
static inline u16 prcmu_get_reset_code(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_ac_wake_req(void) {}
|
||||
|
||||
static inline void prcmu_ac_sleep_req(void) {}
|
||||
|
||||
static inline void prcmu_modem_reset(void) {}
|
||||
|
||||
static inline bool prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int prcmu_set_display_clocks(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_disable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_enable_dsipll(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
|
||||
|
||||
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
|
||||
{
|
||||
*buf = NULL;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* PRCMU QoS APE OPP class */
|
||||
#define PRCMU_QOS_APE_OPP 1
|
||||
#define PRCMU_QOS_DDR_OPP 2
|
||||
#define PRCMU_QOS_DEFAULT_VALUE -1
|
||||
|
||||
#ifdef CONFIG_UX500_PRCMU_QOS_POWER
|
||||
|
||||
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
|
||||
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
|
||||
void prcmu_qos_force_opp(int, s32);
|
||||
int prcmu_qos_requirement(int pm_qos_class);
|
||||
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
|
||||
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
|
||||
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
|
||||
int prcmu_qos_add_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier);
|
||||
int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier);
|
||||
|
||||
#else
|
||||
|
||||
static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
|
||||
|
||||
static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
|
||||
|
||||
static inline int prcmu_qos_requirement(int prcmu_qos_class)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
|
||||
char *name, s32 value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
|
||||
char *name, s32 new_value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
||||
struct notifier_block *notifier)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_PRCMU_H */
|
||||
456
include/linux/mfd/intel_msic.h
Normal file
456
include/linux/mfd/intel_msic.h
Normal file
@@ -0,0 +1,456 @@
|
||||
/*
|
||||
* include/linux/mfd/intel_msic.h - Core interface for Intel MSIC
|
||||
*
|
||||
* Copyright (C) 2011, Intel Corporation
|
||||
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_INTEL_MSIC_H__
|
||||
#define __LINUX_MFD_INTEL_MSIC_H__
|
||||
|
||||
/* ID */
|
||||
#define INTEL_MSIC_ID0 0x000 /* RO */
|
||||
#define INTEL_MSIC_ID1 0x001 /* RO */
|
||||
|
||||
/* IRQ */
|
||||
#define INTEL_MSIC_IRQLVL1 0x002
|
||||
#define INTEL_MSIC_ADC1INT 0x003
|
||||
#define INTEL_MSIC_CCINT 0x004
|
||||
#define INTEL_MSIC_PWRSRCINT 0x005
|
||||
#define INTEL_MSIC_PWRSRCINT1 0x006
|
||||
#define INTEL_MSIC_CHRINT 0x007
|
||||
#define INTEL_MSIC_CHRINT1 0x008
|
||||
#define INTEL_MSIC_RTCIRQ 0x009
|
||||
#define INTEL_MSIC_GPIO0LVIRQ 0x00a
|
||||
#define INTEL_MSIC_GPIO1LVIRQ 0x00b
|
||||
#define INTEL_MSIC_GPIOHVIRQ 0x00c
|
||||
#define INTEL_MSIC_VRINT 0x00d
|
||||
#define INTEL_MSIC_OCAUDIO 0x00e
|
||||
#define INTEL_MSIC_ACCDET 0x00f
|
||||
#define INTEL_MSIC_RESETIRQ1 0x010
|
||||
#define INTEL_MSIC_RESETIRQ2 0x011
|
||||
#define INTEL_MSIC_MADC1INT 0x012
|
||||
#define INTEL_MSIC_MCCINT 0x013
|
||||
#define INTEL_MSIC_MPWRSRCINT 0x014
|
||||
#define INTEL_MSIC_MPWRSRCINT1 0x015
|
||||
#define INTEL_MSIC_MCHRINT 0x016
|
||||
#define INTEL_MSIC_MCHRINT1 0x017
|
||||
#define INTEL_MSIC_RTCIRQMASK 0x018
|
||||
#define INTEL_MSIC_GPIO0LVIRQMASK 0x019
|
||||
#define INTEL_MSIC_GPIO1LVIRQMASK 0x01a
|
||||
#define INTEL_MSIC_GPIOHVIRQMASK 0x01b
|
||||
#define INTEL_MSIC_VRINTMASK 0x01c
|
||||
#define INTEL_MSIC_OCAUDIOMASK 0x01d
|
||||
#define INTEL_MSIC_ACCDETMASK 0x01e
|
||||
#define INTEL_MSIC_RESETIRQ1MASK 0x01f
|
||||
#define INTEL_MSIC_RESETIRQ2MASK 0x020
|
||||
#define INTEL_MSIC_IRQLVL1MSK 0x021
|
||||
#define INTEL_MSIC_PBCONFIG 0x03e
|
||||
#define INTEL_MSIC_PBSTATUS 0x03f /* RO */
|
||||
|
||||
/* GPIO */
|
||||
#define INTEL_MSIC_GPIO0LV7CTLO 0x040
|
||||
#define INTEL_MSIC_GPIO0LV6CTLO 0x041
|
||||
#define INTEL_MSIC_GPIO0LV5CTLO 0x042
|
||||
#define INTEL_MSIC_GPIO0LV4CTLO 0x043
|
||||
#define INTEL_MSIC_GPIO0LV3CTLO 0x044
|
||||
#define INTEL_MSIC_GPIO0LV2CTLO 0x045
|
||||
#define INTEL_MSIC_GPIO0LV1CTLO 0x046
|
||||
#define INTEL_MSIC_GPIO0LV0CTLO 0x047
|
||||
#define INTEL_MSIC_GPIO1LV7CTLOS 0x048
|
||||
#define INTEL_MSIC_GPIO1LV6CTLO 0x049
|
||||
#define INTEL_MSIC_GPIO1LV5CTLO 0x04a
|
||||
#define INTEL_MSIC_GPIO1LV4CTLO 0x04b
|
||||
#define INTEL_MSIC_GPIO1LV3CTLO 0x04c
|
||||
#define INTEL_MSIC_GPIO1LV2CTLO 0x04d
|
||||
#define INTEL_MSIC_GPIO1LV1CTLO 0x04e
|
||||
#define INTEL_MSIC_GPIO1LV0CTLO 0x04f
|
||||
#define INTEL_MSIC_GPIO0LV7CTLI 0x050
|
||||
#define INTEL_MSIC_GPIO0LV6CTLI 0x051
|
||||
#define INTEL_MSIC_GPIO0LV5CTLI 0x052
|
||||
#define INTEL_MSIC_GPIO0LV4CTLI 0x053
|
||||
#define INTEL_MSIC_GPIO0LV3CTLI 0x054
|
||||
#define INTEL_MSIC_GPIO0LV2CTLI 0x055
|
||||
#define INTEL_MSIC_GPIO0LV1CTLI 0x056
|
||||
#define INTEL_MSIC_GPIO0LV0CTLI 0x057
|
||||
#define INTEL_MSIC_GPIO1LV7CTLIS 0x058
|
||||
#define INTEL_MSIC_GPIO1LV6CTLI 0x059
|
||||
#define INTEL_MSIC_GPIO1LV5CTLI 0x05a
|
||||
#define INTEL_MSIC_GPIO1LV4CTLI 0x05b
|
||||
#define INTEL_MSIC_GPIO1LV3CTLI 0x05c
|
||||
#define INTEL_MSIC_GPIO1LV2CTLI 0x05d
|
||||
#define INTEL_MSIC_GPIO1LV1CTLI 0x05e
|
||||
#define INTEL_MSIC_GPIO1LV0CTLI 0x05f
|
||||
#define INTEL_MSIC_PWM0CLKDIV1 0x061
|
||||
#define INTEL_MSIC_PWM0CLKDIV0 0x062
|
||||
#define INTEL_MSIC_PWM1CLKDIV1 0x063
|
||||
#define INTEL_MSIC_PWM1CLKDIV0 0x064
|
||||
#define INTEL_MSIC_PWM2CLKDIV1 0x065
|
||||
#define INTEL_MSIC_PWM2CLKDIV0 0x066
|
||||
#define INTEL_MSIC_PWM0DUTYCYCLE 0x067
|
||||
#define INTEL_MSIC_PWM1DUTYCYCLE 0x068
|
||||
#define INTEL_MSIC_PWM2DUTYCYCLE 0x069
|
||||
#define INTEL_MSIC_GPIO0HV3CTLO 0x06d
|
||||
#define INTEL_MSIC_GPIO0HV2CTLO 0x06e
|
||||
#define INTEL_MSIC_GPIO0HV1CTLO 0x06f
|
||||
#define INTEL_MSIC_GPIO0HV0CTLO 0x070
|
||||
#define INTEL_MSIC_GPIO1HV3CTLO 0x071
|
||||
#define INTEL_MSIC_GPIO1HV2CTLO 0x072
|
||||
#define INTEL_MSIC_GPIO1HV1CTLO 0x073
|
||||
#define INTEL_MSIC_GPIO1HV0CTLO 0x074
|
||||
#define INTEL_MSIC_GPIO0HV3CTLI 0x075
|
||||
#define INTEL_MSIC_GPIO0HV2CTLI 0x076
|
||||
#define INTEL_MSIC_GPIO0HV1CTLI 0x077
|
||||
#define INTEL_MSIC_GPIO0HV0CTLI 0x078
|
||||
#define INTEL_MSIC_GPIO1HV3CTLI 0x079
|
||||
#define INTEL_MSIC_GPIO1HV2CTLI 0x07a
|
||||
#define INTEL_MSIC_GPIO1HV1CTLI 0x07b
|
||||
#define INTEL_MSIC_GPIO1HV0CTLI 0x07c
|
||||
|
||||
/* SVID */
|
||||
#define INTEL_MSIC_SVIDCTRL0 0x080
|
||||
#define INTEL_MSIC_SVIDCTRL1 0x081
|
||||
#define INTEL_MSIC_SVIDCTRL2 0x082
|
||||
#define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */
|
||||
#define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */
|
||||
#define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */
|
||||
#define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */
|
||||
#define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087
|
||||
#define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088
|
||||
#define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089
|
||||
#define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a
|
||||
#define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b
|
||||
#define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c
|
||||
#define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */
|
||||
#define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */
|
||||
#define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */
|
||||
#define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */
|
||||
#define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */
|
||||
#define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */
|
||||
#define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */
|
||||
#define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */
|
||||
|
||||
/* VREG */
|
||||
#define INTEL_MSIC_VCCLATCH 0x0c0
|
||||
#define INTEL_MSIC_VNNLATCH 0x0c1
|
||||
#define INTEL_MSIC_VCCCNT 0x0c2
|
||||
#define INTEL_MSIC_SMPSRAMP 0x0c3
|
||||
#define INTEL_MSIC_VNNCNT 0x0c4
|
||||
#define INTEL_MSIC_VNNAONCNT 0x0c5
|
||||
#define INTEL_MSIC_VCC122AONCNT 0x0c6
|
||||
#define INTEL_MSIC_V180AONCNT 0x0c7
|
||||
#define INTEL_MSIC_V500CNT 0x0c8
|
||||
#define INTEL_MSIC_VIHFCNT 0x0c9
|
||||
#define INTEL_MSIC_LDORAMP1 0x0ca
|
||||
#define INTEL_MSIC_LDORAMP2 0x0cb
|
||||
#define INTEL_MSIC_VCC108AONCNT 0x0cc
|
||||
#define INTEL_MSIC_VCC108ASCNT 0x0cd
|
||||
#define INTEL_MSIC_VCC108CNT 0x0ce
|
||||
#define INTEL_MSIC_VCCA100ASCNT 0x0cf
|
||||
#define INTEL_MSIC_VCCA100CNT 0x0d0
|
||||
#define INTEL_MSIC_VCC180AONCNT 0x0d1
|
||||
#define INTEL_MSIC_VCC180CNT 0x0d2
|
||||
#define INTEL_MSIC_VCC330CNT 0x0d3
|
||||
#define INTEL_MSIC_VUSB330CNT 0x0d4
|
||||
#define INTEL_MSIC_VCCSDIOCNT 0x0d5
|
||||
#define INTEL_MSIC_VPROG1CNT 0x0d6
|
||||
#define INTEL_MSIC_VPROG2CNT 0x0d7
|
||||
#define INTEL_MSIC_VEMMCSCNT 0x0d8
|
||||
#define INTEL_MSIC_VEMMC1CNT 0x0d9
|
||||
#define INTEL_MSIC_VEMMC2CNT 0x0da
|
||||
#define INTEL_MSIC_VAUDACNT 0x0db
|
||||
#define INTEL_MSIC_VHSPCNT 0x0dc
|
||||
#define INTEL_MSIC_VHSNCNT 0x0dd
|
||||
#define INTEL_MSIC_VHDMICNT 0x0de
|
||||
#define INTEL_MSIC_VOTGCNT 0x0df
|
||||
#define INTEL_MSIC_V1P35CNT 0x0e0
|
||||
#define INTEL_MSIC_V330AONCNT 0x0e1
|
||||
|
||||
/* RESET */
|
||||
#define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */
|
||||
#define INTEL_MSIC_ERCONFIG 0x101
|
||||
|
||||
/* BURST */
|
||||
#define INTEL_MSIC_BATCURRENTLIMIT12 0x102
|
||||
#define INTEL_MSIC_BATTIMELIMIT12 0x103
|
||||
#define INTEL_MSIC_BATTIMELIMIT3 0x104
|
||||
#define INTEL_MSIC_BATTIMEDB 0x105
|
||||
#define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106
|
||||
#define INTEL_MSIC_BRSTCONFIGACTIONS 0x107
|
||||
#define INTEL_MSIC_BURSTCONTROLSTATUS 0x108
|
||||
|
||||
/* RTC */
|
||||
#define INTEL_MSIC_RTCB1 0x140 /* RO */
|
||||
#define INTEL_MSIC_RTCB2 0x141 /* RO */
|
||||
#define INTEL_MSIC_RTCB3 0x142 /* RO */
|
||||
#define INTEL_MSIC_RTCB4 0x143 /* RO */
|
||||
#define INTEL_MSIC_RTCOB1 0x144
|
||||
#define INTEL_MSIC_RTCOB2 0x145
|
||||
#define INTEL_MSIC_RTCOB3 0x146
|
||||
#define INTEL_MSIC_RTCOB4 0x147
|
||||
#define INTEL_MSIC_RTCAB1 0x148
|
||||
#define INTEL_MSIC_RTCAB2 0x149
|
||||
#define INTEL_MSIC_RTCAB3 0x14a
|
||||
#define INTEL_MSIC_RTCAB4 0x14b
|
||||
#define INTEL_MSIC_RTCWAB1 0x14c
|
||||
#define INTEL_MSIC_RTCWAB2 0x14d
|
||||
#define INTEL_MSIC_RTCWAB3 0x14e
|
||||
#define INTEL_MSIC_RTCWAB4 0x14f
|
||||
#define INTEL_MSIC_RTCSC1 0x150
|
||||
#define INTEL_MSIC_RTCSC2 0x151
|
||||
#define INTEL_MSIC_RTCSC3 0x152
|
||||
#define INTEL_MSIC_RTCSC4 0x153
|
||||
#define INTEL_MSIC_RTCSTATUS 0x154 /* RO */
|
||||
#define INTEL_MSIC_RTCCONFIG1 0x155
|
||||
#define INTEL_MSIC_RTCCONFIG2 0x156
|
||||
|
||||
/* CHARGER */
|
||||
#define INTEL_MSIC_BDTIMER 0x180
|
||||
#define INTEL_MSIC_BATTRMV 0x181
|
||||
#define INTEL_MSIC_VBUSDET 0x182
|
||||
#define INTEL_MSIC_VBUSDET1 0x183
|
||||
#define INTEL_MSIC_ADPHVDET 0x184
|
||||
#define INTEL_MSIC_ADPLVDET 0x185
|
||||
#define INTEL_MSIC_ADPDETDBDM 0x186
|
||||
#define INTEL_MSIC_LOWBATTDET 0x187
|
||||
#define INTEL_MSIC_CHRCTRL 0x188
|
||||
#define INTEL_MSIC_CHRCVOLTAGE 0x189
|
||||
#define INTEL_MSIC_CHRCCURRENT 0x18a
|
||||
#define INTEL_MSIC_SPCHARGER 0x18b
|
||||
#define INTEL_MSIC_CHRTTIME 0x18c
|
||||
#define INTEL_MSIC_CHRCTRL1 0x18d
|
||||
#define INTEL_MSIC_PWRSRCLMT 0x18e
|
||||
#define INTEL_MSIC_CHRSTWDT 0x18f
|
||||
#define INTEL_MSIC_WDTWRITE 0x190 /* WO */
|
||||
#define INTEL_MSIC_CHRSAFELMT 0x191
|
||||
#define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */
|
||||
#define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */
|
||||
#define INTEL_MSIC_CHRLEDPWM 0x194
|
||||
#define INTEL_MSIC_CHRLEDCTRL 0x195
|
||||
|
||||
/* ADC */
|
||||
#define INTEL_MSIC_ADC1CNTL1 0x1c0
|
||||
#define INTEL_MSIC_ADC1CNTL2 0x1c1
|
||||
#define INTEL_MSIC_ADC1CNTL3 0x1c2
|
||||
#define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */
|
||||
#define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */
|
||||
#define INTEL_MSIC_ADC1ADDR0 0x1c5
|
||||
#define INTEL_MSIC_ADC1ADDR1 0x1c6
|
||||
#define INTEL_MSIC_ADC1ADDR2 0x1c7
|
||||
#define INTEL_MSIC_ADC1ADDR3 0x1c8
|
||||
#define INTEL_MSIC_ADC1ADDR4 0x1c9
|
||||
#define INTEL_MSIC_ADC1ADDR5 0x1ca
|
||||
#define INTEL_MSIC_ADC1ADDR6 0x1cb
|
||||
#define INTEL_MSIC_ADC1ADDR7 0x1cc
|
||||
#define INTEL_MSIC_ADC1ADDR8 0x1cd
|
||||
#define INTEL_MSIC_ADC1ADDR9 0x1ce
|
||||
#define INTEL_MSIC_ADC1ADDR10 0x1cf
|
||||
#define INTEL_MSIC_ADC1ADDR11 0x1d0
|
||||
#define INTEL_MSIC_ADC1ADDR12 0x1d1
|
||||
#define INTEL_MSIC_ADC1ADDR13 0x1d2
|
||||
#define INTEL_MSIC_ADC1ADDR14 0x1d3
|
||||
#define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */
|
||||
#define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */
|
||||
#define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */
|
||||
#define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */
|
||||
#define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */
|
||||
#define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */
|
||||
#define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */
|
||||
#define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */
|
||||
#define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */
|
||||
#define INTEL_MSIC_ADC1BI3H 0x200 /* RO */
|
||||
#define INTEL_MSIC_ADC1BI3L 0x201 /* RO */
|
||||
#define INTEL_MSIC_CCCNTL 0x202
|
||||
#define INTEL_MSIC_CCOFFSETH 0x203 /* RO */
|
||||
#define INTEL_MSIC_CCOFFSETL 0x204 /* RO */
|
||||
#define INTEL_MSIC_CCADCHA 0x205 /* RO */
|
||||
#define INTEL_MSIC_CCADCLA 0x206 /* RO */
|
||||
|
||||
/* AUDIO */
|
||||
#define INTEL_MSIC_AUDPLLCTRL 0x240
|
||||
#define INTEL_MSIC_DMICBUF0123 0x241
|
||||
#define INTEL_MSIC_DMICBUF45 0x242
|
||||
#define INTEL_MSIC_DMICGPO 0x244
|
||||
#define INTEL_MSIC_DMICMUX 0x245
|
||||
#define INTEL_MSIC_DMICCLK 0x246
|
||||
#define INTEL_MSIC_MICBIAS 0x247
|
||||
#define INTEL_MSIC_ADCCONFIG 0x248
|
||||
#define INTEL_MSIC_MICAMP1 0x249
|
||||
#define INTEL_MSIC_MICAMP2 0x24a
|
||||
#define INTEL_MSIC_NOISEMUX 0x24b
|
||||
#define INTEL_MSIC_AUDIOMUX12 0x24c
|
||||
#define INTEL_MSIC_AUDIOMUX34 0x24d
|
||||
#define INTEL_MSIC_AUDIOSINC 0x24e
|
||||
#define INTEL_MSIC_AUDIOTXEN 0x24f
|
||||
#define INTEL_MSIC_HSEPRXCTRL 0x250
|
||||
#define INTEL_MSIC_IHFRXCTRL 0x251
|
||||
#define INTEL_MSIC_VOICETXVOL 0x252
|
||||
#define INTEL_MSIC_SIDETONEVOL 0x253
|
||||
#define INTEL_MSIC_MUSICSHARVOL 0x254
|
||||
#define INTEL_MSIC_VOICETXCTRL 0x255
|
||||
#define INTEL_MSIC_HSMIXER 0x256
|
||||
#define INTEL_MSIC_DACCONFIG 0x257
|
||||
#define INTEL_MSIC_SOFTMUTE 0x258
|
||||
#define INTEL_MSIC_HSLVOLCTRL 0x259
|
||||
#define INTEL_MSIC_HSRVOLCTRL 0x25a
|
||||
#define INTEL_MSIC_IHFLVOLCTRL 0x25b
|
||||
#define INTEL_MSIC_IHFRVOLCTRL 0x25c
|
||||
#define INTEL_MSIC_DRIVEREN 0x25d
|
||||
#define INTEL_MSIC_LINEOUTCTRL 0x25e
|
||||
#define INTEL_MSIC_VIB1CTRL1 0x25f
|
||||
#define INTEL_MSIC_VIB1CTRL2 0x260
|
||||
#define INTEL_MSIC_VIB1CTRL3 0x261
|
||||
#define INTEL_MSIC_VIB1SPIPCM_1 0x262
|
||||
#define INTEL_MSIC_VIB1SPIPCM_2 0x263
|
||||
#define INTEL_MSIC_VIB1CTRL5 0x264
|
||||
#define INTEL_MSIC_VIB2CTRL1 0x265
|
||||
#define INTEL_MSIC_VIB2CTRL2 0x266
|
||||
#define INTEL_MSIC_VIB2CTRL3 0x267
|
||||
#define INTEL_MSIC_VIB2SPIPCM_1 0x268
|
||||
#define INTEL_MSIC_VIB2SPIPCM_2 0x269
|
||||
#define INTEL_MSIC_VIB2CTRL5 0x26a
|
||||
#define INTEL_MSIC_BTNCTRL1 0x26b
|
||||
#define INTEL_MSIC_BTNCTRL2 0x26c
|
||||
#define INTEL_MSIC_PCM1TXSLOT01 0x26d
|
||||
#define INTEL_MSIC_PCM1TXSLOT23 0x26e
|
||||
#define INTEL_MSIC_PCM1TXSLOT45 0x26f
|
||||
#define INTEL_MSIC_PCM1RXSLOT0123 0x270
|
||||
#define INTEL_MSIC_PCM1RXSLOT045 0x271
|
||||
#define INTEL_MSIC_PCM2TXSLOT01 0x272
|
||||
#define INTEL_MSIC_PCM2TXSLOT23 0x273
|
||||
#define INTEL_MSIC_PCM2TXSLOT45 0x274
|
||||
#define INTEL_MSIC_PCM2RXSLOT01 0x275
|
||||
#define INTEL_MSIC_PCM2RXSLOT23 0x276
|
||||
#define INTEL_MSIC_PCM2RXSLOT45 0x277
|
||||
#define INTEL_MSIC_PCM1CTRL1 0x278
|
||||
#define INTEL_MSIC_PCM1CTRL2 0x279
|
||||
#define INTEL_MSIC_PCM1CTRL3 0x27a
|
||||
#define INTEL_MSIC_PCM2CTRL1 0x27b
|
||||
#define INTEL_MSIC_PCM2CTRL2 0x27c
|
||||
|
||||
/* HDMI */
|
||||
#define INTEL_MSIC_HDMIPUEN 0x280
|
||||
#define INTEL_MSIC_HDMISTATUS 0x281 /* RO */
|
||||
|
||||
/* Physical address of the start of the MSIC interrupt tree in SRAM */
|
||||
#define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0
|
||||
|
||||
/**
|
||||
* struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver
|
||||
* @gpio_base: base number for the GPIOs
|
||||
*/
|
||||
struct intel_msic_gpio_pdata {
|
||||
unsigned gpio_base;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver
|
||||
* @gpio: GPIO number used for OCD interrupts
|
||||
*
|
||||
* The MSIC MFD driver converts @gpio into an IRQ number and passes it to
|
||||
* the OCD driver as %IORESOURCE_IRQ.
|
||||
*/
|
||||
struct intel_msic_ocd_pdata {
|
||||
unsigned gpio;
|
||||
};
|
||||
|
||||
/* MSIC embedded blocks (subdevices) */
|
||||
enum intel_msic_block {
|
||||
INTEL_MSIC_BLOCK_TOUCH,
|
||||
INTEL_MSIC_BLOCK_ADC,
|
||||
INTEL_MSIC_BLOCK_BATTERY,
|
||||
INTEL_MSIC_BLOCK_GPIO,
|
||||
INTEL_MSIC_BLOCK_AUDIO,
|
||||
INTEL_MSIC_BLOCK_HDMI,
|
||||
INTEL_MSIC_BLOCK_THERMAL,
|
||||
INTEL_MSIC_BLOCK_POWER_BTN,
|
||||
INTEL_MSIC_BLOCK_OCD,
|
||||
|
||||
INTEL_MSIC_BLOCK_LAST,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct intel_msic_platform_data - platform data for the MSIC driver
|
||||
* @irq: array of interrupt numbers, one per device. If @irq is set to %0
|
||||
* for a given block, the corresponding platform device is not
|
||||
* created. For devices which don't have an interrupt, use %0xff
|
||||
* (this is same as in SFI spec).
|
||||
* @gpio: platform data for the MSIC GPIO driver
|
||||
* @ocd: platform data for the MSIC OCD driver
|
||||
*
|
||||
* Once the MSIC driver is initialized, the register interface is ready to
|
||||
* use. All the platform devices for subdevices are created after the
|
||||
* register interface is ready so that we can guarantee its availability to
|
||||
* the subdevice drivers.
|
||||
*
|
||||
* Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ
|
||||
* resources of the created platform device.
|
||||
*/
|
||||
struct intel_msic_platform_data {
|
||||
int irq[INTEL_MSIC_BLOCK_LAST];
|
||||
struct intel_msic_gpio_pdata *gpio;
|
||||
struct intel_msic_ocd_pdata *ocd;
|
||||
};
|
||||
|
||||
struct intel_msic;
|
||||
|
||||
extern int intel_msic_reg_read(unsigned short reg, u8 *val);
|
||||
extern int intel_msic_reg_write(unsigned short reg, u8 val);
|
||||
extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask);
|
||||
extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count);
|
||||
extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count);
|
||||
|
||||
/*
|
||||
* pdev_to_intel_msic - gets an MSIC instance from the platform device
|
||||
* @pdev: platform device pointer
|
||||
*
|
||||
* The client drivers need to have pointer to the MSIC instance if they
|
||||
* want to call intel_msic_irq_read(). This macro can be used for
|
||||
* convenience to get the MSIC pointer from @pdev where needed. This is
|
||||
* _only_ valid for devices which are managed by the MSIC.
|
||||
*/
|
||||
#define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent))
|
||||
|
||||
extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg,
|
||||
u8 *val);
|
||||
|
||||
#endif /* __LINUX_MFD_INTEL_MSIC_H__ */
|
||||
@@ -326,7 +326,6 @@ struct max8997_dev {
|
||||
int irq;
|
||||
int ono;
|
||||
int irq_base;
|
||||
bool wakeup;
|
||||
struct mutex irqlock;
|
||||
int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
|
||||
int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
|
||||
|
||||
@@ -12,117 +12,6 @@
|
||||
|
||||
#include <linux/mfd/mc13xxx.h>
|
||||
|
||||
struct mc13783;
|
||||
|
||||
struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783);
|
||||
|
||||
static inline void mc13783_lock(struct mc13783 *mc13783)
|
||||
{
|
||||
mc13xxx_lock(mc13783_to_mc13xxx(mc13783));
|
||||
}
|
||||
|
||||
static inline void mc13783_unlock(struct mc13783 *mc13783)
|
||||
{
|
||||
mc13xxx_unlock(mc13783_to_mc13xxx(mc13783));
|
||||
}
|
||||
|
||||
static inline int mc13783_reg_read(struct mc13783 *mc13783,
|
||||
unsigned int offset, u32 *val)
|
||||
{
|
||||
return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val);
|
||||
}
|
||||
|
||||
static inline int mc13783_reg_write(struct mc13783 *mc13783,
|
||||
unsigned int offset, u32 val)
|
||||
{
|
||||
return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val);
|
||||
}
|
||||
|
||||
static inline int mc13783_reg_rmw(struct mc13783 *mc13783,
|
||||
unsigned int offset, u32 mask, u32 val)
|
||||
{
|
||||
return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val);
|
||||
}
|
||||
|
||||
static inline int mc13783_get_flags(struct mc13783 *mc13783)
|
||||
{
|
||||
return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783));
|
||||
}
|
||||
|
||||
static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq,
|
||||
irq_handler_t handler, const char *name, void *dev)
|
||||
{
|
||||
return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq,
|
||||
handler, name, dev);
|
||||
}
|
||||
|
||||
static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
|
||||
irq_handler_t handler, const char *name, void *dev)
|
||||
{
|
||||
return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq,
|
||||
handler, name, dev);
|
||||
}
|
||||
|
||||
static inline int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
|
||||
{
|
||||
return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev);
|
||||
}
|
||||
|
||||
static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
|
||||
{
|
||||
return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq);
|
||||
}
|
||||
|
||||
static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
|
||||
{
|
||||
return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq);
|
||||
}
|
||||
static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq,
|
||||
int *enabled, int *pending)
|
||||
{
|
||||
return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783),
|
||||
irq, enabled, pending);
|
||||
}
|
||||
|
||||
static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
|
||||
{
|
||||
return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq);
|
||||
}
|
||||
|
||||
#define MC13783_ADC0 43
|
||||
#define MC13783_ADC0_ADREFEN (1 << 10)
|
||||
#define MC13783_ADC0_ADREFMODE (1 << 11)
|
||||
#define MC13783_ADC0_TSMOD0 (1 << 12)
|
||||
#define MC13783_ADC0_TSMOD1 (1 << 13)
|
||||
#define MC13783_ADC0_TSMOD2 (1 << 14)
|
||||
#define MC13783_ADC0_ADINC1 (1 << 16)
|
||||
#define MC13783_ADC0_ADINC2 (1 << 17)
|
||||
|
||||
#define MC13783_ADC0_TSMOD_MASK (MC13783_ADC0_TSMOD0 | \
|
||||
MC13783_ADC0_TSMOD1 | \
|
||||
MC13783_ADC0_TSMOD2)
|
||||
|
||||
#define mc13783_regulator_init_data mc13xxx_regulator_init_data
|
||||
#define mc13783_regulator_platform_data mc13xxx_regulator_platform_data
|
||||
#define mc13783_led_platform_data mc13xxx_led_platform_data
|
||||
#define mc13783_leds_platform_data mc13xxx_leds_platform_data
|
||||
|
||||
#define mc13783_platform_data mc13xxx_platform_data
|
||||
#define MC13783_USE_TOUCHSCREEN MC13XXX_USE_TOUCHSCREEN
|
||||
#define MC13783_USE_CODEC MC13XXX_USE_CODEC
|
||||
#define MC13783_USE_ADC MC13XXX_USE_ADC
|
||||
#define MC13783_USE_RTC MC13XXX_USE_RTC
|
||||
#define MC13783_USE_REGULATOR MC13XXX_USE_REGULATOR
|
||||
#define MC13783_USE_LED MC13XXX_USE_LED
|
||||
|
||||
#define MC13783_ADC_MODE_TS 1
|
||||
#define MC13783_ADC_MODE_SINGLE_CHAN 2
|
||||
#define MC13783_ADC_MODE_MULT_CHAN 3
|
||||
|
||||
int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
|
||||
unsigned int channel, unsigned int *sample);
|
||||
|
||||
|
||||
#define MC13783_REG_SW1A 0
|
||||
#define MC13783_REG_SW1B 1
|
||||
#define MC13783_REG_SW2A 2
|
||||
|
||||
@@ -37,6 +37,9 @@ int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
|
||||
|
||||
int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
|
||||
|
||||
int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
|
||||
unsigned int mode, unsigned int channel, unsigned int *sample);
|
||||
|
||||
#define MC13XXX_IRQ_ADCDONE 0
|
||||
#define MC13XXX_IRQ_ADCBISDONE 1
|
||||
#define MC13XXX_IRQ_TS 2
|
||||
@@ -137,17 +140,48 @@ struct mc13xxx_leds_platform_data {
|
||||
char tc3_period;
|
||||
};
|
||||
|
||||
struct mc13xxx_buttons_platform_data {
|
||||
#define MC13783_BUTTON_DBNC_0MS 0
|
||||
#define MC13783_BUTTON_DBNC_30MS 1
|
||||
#define MC13783_BUTTON_DBNC_150MS 2
|
||||
#define MC13783_BUTTON_DBNC_750MS 3
|
||||
#define MC13783_BUTTON_ENABLE (1 << 2)
|
||||
#define MC13783_BUTTON_POL_INVERT (1 << 3)
|
||||
#define MC13783_BUTTON_RESET_EN (1 << 4)
|
||||
int b1on_flags;
|
||||
unsigned short b1on_key;
|
||||
int b2on_flags;
|
||||
unsigned short b2on_key;
|
||||
int b3on_flags;
|
||||
unsigned short b3on_key;
|
||||
};
|
||||
|
||||
struct mc13xxx_platform_data {
|
||||
#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
|
||||
#define MC13XXX_USE_CODEC (1 << 1)
|
||||
#define MC13XXX_USE_ADC (1 << 2)
|
||||
#define MC13XXX_USE_RTC (1 << 3)
|
||||
#define MC13XXX_USE_REGULATOR (1 << 4)
|
||||
#define MC13XXX_USE_LED (1 << 5)
|
||||
unsigned int flags;
|
||||
|
||||
struct mc13xxx_regulator_platform_data regulators;
|
||||
struct mc13xxx_leds_platform_data *leds;
|
||||
struct mc13xxx_buttons_platform_data *buttons;
|
||||
};
|
||||
|
||||
#define MC13XXX_ADC_MODE_TS 1
|
||||
#define MC13XXX_ADC_MODE_SINGLE_CHAN 2
|
||||
#define MC13XXX_ADC_MODE_MULT_CHAN 3
|
||||
|
||||
#define MC13XXX_ADC0 43
|
||||
#define MC13XXX_ADC0_ADREFEN (1 << 10)
|
||||
#define MC13XXX_ADC0_TSMOD0 (1 << 12)
|
||||
#define MC13XXX_ADC0_TSMOD1 (1 << 13)
|
||||
#define MC13XXX_ADC0_TSMOD2 (1 << 14)
|
||||
#define MC13XXX_ADC0_ADINC1 (1 << 16)
|
||||
#define MC13XXX_ADC0_ADINC2 (1 << 17)
|
||||
|
||||
#define MC13XXX_ADC0_TSMOD_MASK (MC13XXX_ADC0_TSMOD0 | \
|
||||
MC13XXX_ADC0_TSMOD1 | \
|
||||
MC13XXX_ADC0_TSMOD2)
|
||||
|
||||
#endif /* ifndef __LINUX_MFD_MC13XXX_H */
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
#include <linux/mfd/pcf50633/backlight.h>
|
||||
|
||||
struct pcf50633;
|
||||
struct regmap;
|
||||
|
||||
#define PCF50633_NUM_REGULATORS 11
|
||||
|
||||
@@ -134,7 +135,7 @@ enum {
|
||||
|
||||
struct pcf50633 {
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c_client;
|
||||
struct regmap *regmap;
|
||||
|
||||
struct pcf50633_platform_data *pdata;
|
||||
int irq;
|
||||
|
||||
@@ -382,6 +382,7 @@ struct wm831x {
|
||||
|
||||
/* Used by the interrupt controller code to post writes */
|
||||
int gpio_update[WM831X_NUM_GPIO_REGS];
|
||||
bool gpio_level[WM831X_NUM_GPIO_REGS];
|
||||
|
||||
struct mutex auxadc_lock;
|
||||
struct list_head auxadc_pending;
|
||||
|
||||
@@ -59,6 +59,8 @@ struct wm8994 {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
|
||||
bool ldo_ena_always_driven;
|
||||
|
||||
int gpio_base;
|
||||
int irq_base;
|
||||
|
||||
|
||||
@@ -167,6 +167,13 @@ struct wm8994_pdata {
|
||||
|
||||
/* WM8958 microphone bias configuration */
|
||||
int micbias[2];
|
||||
|
||||
/* Disable the internal pull downs on the LDOs if they are
|
||||
* always driven (eg, connected to an always on supply or
|
||||
* GPIO that always drives an output. If they float power
|
||||
* consumption will rise.
|
||||
*/
|
||||
bool ldo_ena_always_driven;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user