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x86, cacheinfo: Fixup L3 cache information for AMD multi-node processors

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L3 cache size, associativity and shared_cpu information need to be
adapted to show information for an internal node instead of the
entire physical package.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Andreas Herrmann
2009-09-03 09:41:19 +02:00
committed by H. Peter Anvin
parent 4a376ec3a2
commit a326e948c5
1 changed files with 22 additions and 10 deletions
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32
arch/x86/kernel/cpu/intel_cacheinfo.c
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@@ -241,7 +241,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
case 0: case 0:
if (!l1->val) if (!l1->val)
return; return;
assoc = l1->assoc; assoc = assocs[l1->assoc];
line_size = l1->line_size; line_size = l1->line_size;
lines_per_tag = l1->lines_per_tag; lines_per_tag = l1->lines_per_tag;
size_in_kb = l1->size_in_kb; size_in_kb = l1->size_in_kb;
@@ -249,7 +249,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
case 2: case 2:
if (!l2.val) if (!l2.val)
return; return;
assoc = l2.assoc; assoc = assocs[l2.assoc];
line_size = l2.line_size; line_size = l2.line_size;
lines_per_tag = l2.lines_per_tag; lines_per_tag = l2.lines_per_tag;
/* cpu_data has errata corrections for K7 applied */ /* cpu_data has errata corrections for K7 applied */
@@ -258,10 +258,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
case 3: case 3:
if (!l3.val) if (!l3.val)
return; return;
assoc = l3.assoc; assoc = assocs[l3.assoc];
line_size = l3.line_size; line_size = l3.line_size;
lines_per_tag = l3.lines_per_tag; lines_per_tag = l3.lines_per_tag;
size_in_kb = l3.size_encoded * 512; size_in_kb = l3.size_encoded * 512;
if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
size_in_kb = size_in_kb >> 1;
assoc = assoc >> 1;
}
break; break;
default: default:
return; return;
@@ -270,18 +274,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
eax->split.is_self_initializing = 1; eax->split.is_self_initializing = 1;
eax->split.type = types[leaf]; eax->split.type = types[leaf];
eax->split.level = levels[leaf]; eax->split.level = levels[leaf];
if (leaf == 3) eax->split.num_threads_sharing = 0;
eax->split.num_threads_sharing =
current_cpu_data.x86_max_cores - 1;
else
eax->split.num_threads_sharing = 0;
eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1; eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
if (assoc == 0xf) if (assoc == 0xffff)
eax->split.is_fully_associative = 1; eax->split.is_fully_associative = 1;
ebx->split.coherency_line_size = line_size - 1; ebx->split.coherency_line_size = line_size - 1;
ebx->split.ways_of_associativity = assocs[assoc] - 1; ebx->split.ways_of_associativity = assoc - 1;
ebx->split.physical_line_partition = lines_per_tag - 1; ebx->split.physical_line_partition = lines_per_tag - 1;
ecx->split.number_of_sets = (size_in_kb * 1024) / line_size / ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
(ebx->split.ways_of_associativity + 1) - 1; (ebx->split.ways_of_associativity + 1) - 1;
@@ -522,6 +522,18 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
int index_msb, i; int index_msb, i;
struct cpuinfo_x86 *c = &cpu_data(cpu); struct cpuinfo_x86 *c = &cpu_data(cpu);
if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
struct cpuinfo_x86 *d;
for_each_online_cpu(i) {
if (!per_cpu(cpuid4_info, i))
continue;
d = &cpu_data(i);
this_leaf = CPUID4_INFO_IDX(i, index);
cpumask_copy(to_cpumask(this_leaf->shared_cpu_map),
d->llc_shared_map);
}
return;
}
this_leaf = CPUID4_INFO_IDX(cpu, index); this_leaf = CPUID4_INFO_IDX(cpu, index);
num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing; num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;