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ARM: SAMSUNG: cleanup of rtc register definitions

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regs-rtc.h uses a mixture of tabs and spaces and also (x<<y)
to format bits. So, before adding new stuff clean up the formatting
and also add spaces to the bit definitions (i.e. (x << y) )

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
2011-12-24 10:52:10 +09:00
committed by Kukjin Kim
parent 62aa2b537c
commit a51da0444c
1 changed files with 27 additions and 41 deletions
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14
arch/arm/plat-samsung/include/plat/regs-rtc.h
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@@ -20,14 +20,10 @@
#define S3C2410_RTCCON S3C2410_RTCREG(0x40) #define S3C2410_RTCCON S3C2410_RTCREG(0x40)
#define S3C2410_RTCCON_RTCEN (1 << 0) #define S3C2410_RTCCON_RTCEN (1 << 0)
#define S3C2410_RTCCON_CLKSEL (1<<1)
#define S3C2410_RTCCON_CNTSEL (1 << 2) #define S3C2410_RTCCON_CNTSEL (1 << 2)
#define S3C2410_RTCCON_CLKRST (1 << 3) #define S3C2410_RTCCON_CLKRST (1 << 3)
#define S3C64XX_RTCCON_TICEN (1 << 8) #define S3C64XX_RTCCON_TICEN (1 << 8)
#define S3C64XX_RTCCON_TICMSK (0xF<<7)
#define S3C64XX_RTCCON_TICSHT (7)
#define S3C2410_TICNT S3C2410_RTCREG(0x44) #define S3C2410_TICNT S3C2410_RTCREG(0x44)
#define S3C2410_TICNT_ENABLE (1 << 7) #define S3C2410_TICNT_ENABLE (1 << 7)
@@ -40,12 +36,6 @@
#define S3C2410_RTCALM_MINEN (1 << 1) #define S3C2410_RTCALM_MINEN (1 << 1)
#define S3C2410_RTCALM_SECEN (1 << 0) #define S3C2410_RTCALM_SECEN (1 << 0)
#define S3C2410_RTCALM_ALL \
S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
S3C2410_RTCALM_SECEN
#define S3C2410_ALMSEC S3C2410_RTCREG(0x54) #define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
#define S3C2410_ALMMIN S3C2410_RTCREG(0x58) #define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
@@ -54,15 +44,11 @@
#define S3C2410_ALMMON S3C2410_RTCREG(0x64) #define S3C2410_ALMMON S3C2410_RTCREG(0x64)
#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
#define S3C2410_RTCSEC S3C2410_RTCREG(0x70) #define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
#define S3C2410_RTCMIN S3C2410_RTCREG(0x74) #define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
#define S3C2410_RTCMON S3C2410_RTCREG(0x84) #define S3C2410_RTCMON S3C2410_RTCREG(0x84)
#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
#endif /* __ASM_ARCH_REGS_RTC_H */ #endif /* __ASM_ARCH_REGS_RTC_H */