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powerpc: Base support for exceptions using HSRR0/1

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Pass the register type to the prolog, also provides alternate "HV"
version of hardware interrupt (0x500) and adjust LPES accordingly

We tag those interrupts by setting bit 0x2 in the trap number

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2011-04-05 14:20:31 +10:00
parent 2dd60d79e0
commit a5d4f3ad3a
9 changed files with 86 additions and 49 deletions
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3
arch/powerpc/kernel/cpu_setup_power7.S
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@@ -52,13 +52,14 @@ __init_hvmode_206:
__init_LPCR:
/* Setup a sane LPCR:
*
* LPES = 0b11 (SRR0/1 used for 0x500)
* LPES = 0b01 (HSRR0/1 used for 0x500)
* PECE = 0b111
*
* Other bits untouched for now
*/
mfspr r3,SPRN_LPCR
ori r3,r3,(LPCR_LPES0|LPCR_LPES1)
xori r3,r3, LPCR_LPES0
ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
mtspr SPRN_LPCR,r3
isync