V4L/DVB (5119): Various cx2341x documentation updates/fixes.
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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Mauro Carvalho Chehab
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@@ -22,6 +22,8 @@ urged to choose a smaller block size and learn the scatter-gather technique.
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Mailbox #10 is reserved for DMA transfer information.
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Mailbox #10 is reserved for DMA transfer information.
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Note: the hardware expects little-endian data ('intel format').
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Flow
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Flow
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====
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====
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@@ -64,7 +66,7 @@ addresses are the physical memory location of the target DMA buffer.
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Each S-G array element is a struct of three 32-bit words. The first word is
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Each S-G array element is a struct of three 32-bit words. The first word is
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the source address, the second is the destination address. Both take up the
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the source address, the second is the destination address. Both take up the
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entire 32 bits. The lowest 16 bits of the third word is the transfer byte
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entire 32 bits. The lowest 18 bits of the third word is the transfer byte
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count. The high-bit of the third word is the "last" flag. The last-flag tells
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count. The high-bit of the third word is the "last" flag. The last-flag tells
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the card to raise the DMA_DONE interrupt. From hard personal experience, if
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the card to raise the DMA_DONE interrupt. From hard personal experience, if
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you forget to set this bit, the card will still "work" but the stream will
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you forget to set this bit, the card will still "work" but the stream will
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@@ -78,8 +80,8 @@ Array Element:
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- 32-bit Source Address
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- 32-bit Source Address
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- 32-bit Destination Address
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- 32-bit Destination Address
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- 16-bit reserved (high bit is the last flag)
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- 14-bit reserved (high bit is the last flag)
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- 16-bit byte count
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- 18-bit byte count
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DMA Transfer Status
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DMA Transfer Status
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===================
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===================
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@@ -87,8 +89,8 @@ DMA Transfer Status
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Register 0x0004 holds the DMA Transfer Status:
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Register 0x0004 holds the DMA Transfer Status:
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Bit
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Bit
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4 Scatter-Gather array error
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3 DMA write error
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2 DMA read error
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1 write completed
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0 read completed
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0 read completed
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1 write completed
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2 DMA read error
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3 DMA write error
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4 Scatter-Gather array error
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@@ -498,12 +498,14 @@ Name CX2341X_ENC_GET_PREV_DMA_INFO_MB_9
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Enum 203/0xCB
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Enum 203/0xCB
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Description
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Description
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Returns information on the previous DMA transfer in conjunction with
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Returns information on the previous DMA transfer in conjunction with
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bit 27 of the interrupt mask. Uses mailbox 9.
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bit 27 or 18 of the interrupt mask. Uses mailbox 9.
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Result[0]
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Result[0]
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Status bits:
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Status bits:
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Bit 0 set indicates transfer complete
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0 read completed
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Bit 2 set indicates transfer error
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1 write completed
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Bit 4 set indicates linked list error
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2 DMA read error
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3 DMA write error
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4 Scatter-Gather array error
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Result[1]
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Result[1]
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DMA type
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DMA type
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Result[2]
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Result[2]
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@@ -1,6 +1,8 @@
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This document describes the cx2341x memory map and documents some of the register
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This document describes the cx2341x memory map and documents some of the register
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space.
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space.
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Note: the memory long words are little-endian ('intel format').
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Warning! This information was figured out from searching through the memory and
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Warning! This information was figured out from searching through the memory and
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registers, this information may not be correct and is certainly not complete, and
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registers, this information may not be correct and is certainly not complete, and
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was not derived from anything more than searching through the memory space with
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was not derived from anything more than searching through the memory space with
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@@ -67,7 +69,7 @@ DMA Registers 0x000-0xff:
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0x84 - first write linked list reg, for pci memory addr
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0x84 - first write linked list reg, for pci memory addr
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0x88 - first write linked list reg, for length of buffer in memory addr
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0x88 - first write linked list reg, for length of buffer in memory addr
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(|0x80000000 or this for last link)
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(|0x80000000 or this for last link)
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0x8c-0xcc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
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0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
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from linked list addr in reg 0x0c, firmware must push through or
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from linked list addr in reg 0x0c, firmware must push through or
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something.
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something.
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0xe0 - first (and only) read linked list reg, for pci memory addr
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0xe0 - first (and only) read linked list reg, for pci memory addr
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