Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
This commit is contained in:
Linus Torvalds
@ -536,6 +536,49 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
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_clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
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}
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static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
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{
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void __iomem *reg = bank->base;
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int inv = 0;
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u32 l;
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u32 mask;
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switch (bank->method) {
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_MASKIT;
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mask = 0xffff;
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inv = 1;
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break;
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case METHOD_GPIO_1510:
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reg += OMAP1510_GPIO_INT_MASK;
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mask = 0xffff;
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inv = 1;
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break;
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case METHOD_GPIO_1610:
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reg += OMAP1610_GPIO_IRQENABLE1;
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mask = 0xffff;
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break;
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case METHOD_GPIO_730:
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reg += OMAP730_GPIO_INT_MASK;
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mask = 0xffffffff;
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inv = 1;
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break;
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case METHOD_GPIO_24XX:
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reg += OMAP24XX_GPIO_IRQENABLE1;
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mask = 0xffffffff;
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break;
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default:
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BUG();
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return 0;
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}
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l = __raw_readl(reg);
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if (inv)
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l = ~l;
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l &= mask;
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return l;
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}
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static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
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{
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void __iomem *reg = bank->base;
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@ -735,6 +778,8 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
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u32 isr;
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unsigned int gpio_irq;
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struct gpio_bank *bank;
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u32 retrigger = 0;
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int unmasked = 0;
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desc->chip->ack(irq);
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@ -759,18 +804,22 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
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#endif
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while(1) {
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u32 isr_saved, level_mask = 0;
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u32 enabled;
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isr_saved = isr = __raw_readl(isr_reg);
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enabled = _get_gpio_irqbank_mask(bank);
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isr_saved = isr = __raw_readl(isr_reg) & enabled;
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if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
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isr &= 0x0000ffff;
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if (cpu_is_omap24xx())
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if (cpu_is_omap24xx()) {
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level_mask =
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__raw_readl(bank->base +
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OMAP24XX_GPIO_LEVELDETECT0) |
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__raw_readl(bank->base +
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OMAP24XX_GPIO_LEVELDETECT1);
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level_mask &= enabled;
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}
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/* clear edge sensitive interrupts before handler(s) are
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called so that we don't miss any interrupt occurred while
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@ -781,19 +830,54 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
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/* if there is only edge sensitive GPIO pin interrupts
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configured, we could unmask GPIO bank interrupt immediately */
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if (!level_mask)
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if (!level_mask && !unmasked) {
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unmasked = 1;
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desc->chip->unmask(irq);
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}
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isr |= retrigger;
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retrigger = 0;
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if (!isr)
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break;
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gpio_irq = bank->virtual_irq_start;
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for (; isr != 0; isr >>= 1, gpio_irq++) {
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struct irqdesc *d;
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int irq_mask;
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if (!(isr & 1))
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continue;
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d = irq_desc + gpio_irq;
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/* Don't run the handler if it's already running
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* or was disabled lazely.
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*/
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if (unlikely((d->disable_depth || d->running))) {
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irq_mask = 1 <<
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(gpio_irq - bank->virtual_irq_start);
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/* The unmasking will be done by
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* enable_irq in case it is disabled or
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* after returning from the handler if
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* it's already running.
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*/
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_enable_gpio_irqbank(bank, irq_mask, 0);
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if (!d->disable_depth) {
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/* Level triggered interrupts
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* won't ever be reentered
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*/
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BUG_ON(level_mask & irq_mask);
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d->pending = 1;
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}
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continue;
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}
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d->running = 1;
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desc_handle_irq(gpio_irq, d, regs);
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d->running = 0;
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if (unlikely(d->pending && !d->disable_depth)) {
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irq_mask = 1 <<
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(gpio_irq - bank->virtual_irq_start);
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d->pending = 0;
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_enable_gpio_irqbank(bank, irq_mask, 1);
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retrigger |= irq_mask;
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}
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}
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if (cpu_is_omap24xx()) {
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@ -803,13 +887,14 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
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_enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
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}
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/* if bank has any level sensitive GPIO pin interrupt
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configured, we must unmask the bank interrupt only after
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handler(s) are executed in order to avoid spurious bank
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interrupt */
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if (level_mask)
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desc->chip->unmask(irq);
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}
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/* if bank has any level sensitive GPIO pin interrupt
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configured, we must unmask the bank interrupt only after
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handler(s) are executed in order to avoid spurious bank
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interrupt */
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if (!unmasked)
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desc->chip->unmask(irq);
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}
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static void gpio_ack_irq(unsigned int irq)
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