Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
This commit is contained in:
Linus Torvalds
@@ -7,6 +7,7 @@
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* Partial timer rewrite and additional dynamic tick timer support by
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* Tony Lindgen <tony@atomide.com> and
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* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* MPU timer code based on the older MPU timer code for OMAP
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* Copyright (C) 2000 RidgeRun, Inc.
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@@ -49,6 +50,7 @@
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/arch/dmtimer.h>
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struct sys_timer omap_timer;
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@@ -78,18 +80,6 @@ struct sys_timer omap_timer;
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#define OMAP1_32K_TIMER_TVR 0x00
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#define OMAP1_32K_TIMER_TCR 0x04
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/* 24xx specific defines */
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#define OMAP2_GP_TIMER_BASE 0x48028000
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#define CM_CLKSEL_WKUP 0x48008440
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#define GP_TIMER_TIDR 0x00
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#define GP_TIMER_TISR 0x18
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#define GP_TIMER_TIER 0x1c
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#define GP_TIMER_TCLR 0x24
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#define GP_TIMER_TCRR 0x28
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#define GP_TIMER_TLDR 0x2c
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#define GP_TIMER_TTGR 0x30
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#define GP_TIMER_TSICR 0x40
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#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
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/*
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@@ -101,24 +91,55 @@ struct sys_timer omap_timer;
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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#if defined(CONFIG_ARCH_OMAP1)
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static inline void omap_32k_timer_write(int val, int reg)
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{
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if (cpu_class_is_omap1())
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omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
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if (cpu_is_omap24xx())
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omap_writel(val, OMAP2_GP_TIMER_BASE + reg);
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omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
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}
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static inline unsigned long omap_32k_timer_read(int reg)
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{
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if (cpu_class_is_omap1())
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return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
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if (cpu_is_omap24xx())
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return omap_readl(OMAP2_GP_TIMER_BASE + reg);
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return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
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}
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
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omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
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}
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static inline void omap_32k_timer_stop(void)
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{
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omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
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}
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#define omap_32k_timer_ack_irq()
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#elif defined(CONFIG_ARCH_OMAP2)
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static struct omap_dm_timer *gptimer;
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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omap_dm_timer_start(gptimer);
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}
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static inline void omap_32k_timer_stop(void)
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{
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omap_dm_timer_stop(gptimer);
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}
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static inline void omap_32k_timer_ack_irq(void)
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{
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u32 status = omap_dm_timer_read_status(gptimer);
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omap_dm_timer_write_status(gptimer, status);
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}
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#endif
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/*
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* The 32KHz synchronized timer is an additional timer on 16xx.
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* It is always running.
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@@ -128,29 +149,6 @@ static inline unsigned long omap_32k_sync_timer_read(void)
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return omap_readl(TIMER_32K_SYNCHRONIZED);
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}
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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if (cpu_class_is_omap1()) {
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omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
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omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
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}
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if (cpu_is_omap24xx()) {
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omap_32k_timer_write(0xffffffff - load_val, GP_TIMER_TCRR);
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omap_32k_timer_write((1 << 1), GP_TIMER_TIER);
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omap_32k_timer_write((1 << 1) | 1, GP_TIMER_TCLR);
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}
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}
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static inline void omap_32k_timer_stop(void)
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{
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if (cpu_class_is_omap1())
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omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
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if (cpu_is_omap24xx())
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omap_32k_timer_write(0x0, GP_TIMER_TCLR);
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}
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/*
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* Rounds down to nearest usec. Note that this will overflow for larger values.
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*/
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@@ -202,11 +200,7 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
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write_seqlock_irqsave(&xtime_lock, flags);
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if (cpu_is_omap24xx()) {
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u32 status = omap_32k_timer_read(GP_TIMER_TISR);
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omap_32k_timer_write(status, GP_TIMER_TISR);
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}
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omap_32k_timer_ack_irq();
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now = omap_32k_sync_timer_read();
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while ((signed long)(now - omap_32k_last_tick)
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@@ -268,9 +262,6 @@ static struct irqaction omap_32k_timer_irq = {
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.handler = omap_32k_timer_interrupt,
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};
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static struct clk * gpt1_ick;
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static struct clk * gpt1_fck;
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static __init void omap_init_32k_timer(void)
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{
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#ifdef CONFIG_NO_IDLE_HZ
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@@ -279,32 +270,22 @@ static __init void omap_init_32k_timer(void)
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if (cpu_class_is_omap1())
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setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
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if (cpu_is_omap24xx())
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setup_irq(37, &omap_32k_timer_irq);
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omap_timer.offset = omap_32k_timer_gettimeoffset;
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omap_32k_last_tick = omap_32k_sync_timer_read();
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#ifdef CONFIG_ARCH_OMAP2
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/* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
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if (cpu_is_omap24xx()) {
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omap_32k_timer_write(0, GP_TIMER_TCLR);
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omap_writel(0, CM_CLKSEL_WKUP); /* 32KHz clock source */
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gptimer = omap_dm_timer_request_specific(1);
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BUG_ON(gptimer == NULL);
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gpt1_ick = clk_get(NULL, "gpt1_ick");
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if (IS_ERR(gpt1_ick))
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printk(KERN_ERR "Could not get gpt1_ick\n");
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else
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clk_enable(gpt1_ick);
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gpt1_fck = clk_get(NULL, "gpt1_fck");
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if (IS_ERR(gpt1_fck))
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printk(KERN_ERR "Could not get gpt1_fck\n");
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else
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clk_enable(gpt1_fck);
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mdelay(100); /* Wait for clocks to stabilize */
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omap_32k_timer_write(0x7, GP_TIMER_TISR);
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omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
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omap_dm_timer_set_int_enable(gptimer,
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OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
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OMAP_TIMER_INT_MATCH);
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}
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#endif
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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}
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@@ -316,6 +297,9 @@ static __init void omap_init_32k_timer(void)
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*/
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static void __init omap_timer_init(void)
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{
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#ifdef CONFIG_OMAP_DM_TIMER
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omap_dm_timer_init();
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#endif
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omap_init_32k_timer();
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}
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