igb: when number of CPUs > 4 combine tx/rx queues to allow more queues
This patch makes it so that nics such as 82576 and newer can support more hardware queues when there are more than 4 cpus by combining a tx/rx queue pair onto one interrupt so that 8 queue pairs can be supported and thus allow for more queues. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller
parent
115f459a53
commit
a99955fc06
@@ -59,10 +59,10 @@ struct igb_adapter;
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#define MAX_Q_VECTORS 8
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/* Transmit and receive queues */
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#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \
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(adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
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#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
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#define IGB_ABS_MAX_TX_QUEUES 4
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#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
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(hw->mac.type > e1000_82575 ? 8 : 4))
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#define IGB_ABS_MAX_TX_QUEUES 8
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#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
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#define IGB_MAX_VF_MC_ENTRIES 30
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#define IGB_MAX_VF_FUNCTIONS 8
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@@ -315,6 +315,7 @@ struct igb_adapter {
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u16 rx_ring_count;
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unsigned int vfs_allocated_count;
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struct vf_data_storage *vf_data;
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u32 rss_queues;
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};
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#define IGB_FLAG_HAS_MSI (1 << 0)
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