AT91: SAM9G45 - add a separate clock entry for every single TC block
Without this patch you will not be able to register the first block because of the second association call on at91_add_device_tc(). Signed-off-by: Fabian Godehardt <fg@emlix.com> [nicolas.ferre@atmel.com: change tcb1_clk to fake child clock of tcb0_clk] Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
committed by
Nicolas Ferre
parent
5afddee415
commit
ab64511cbb
@@ -121,8 +121,8 @@ static struct clk ssc1_clk = {
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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.type = CLK_TYPE_PERIPHERAL,
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};
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};
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static struct clk tcb_clk = {
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static struct clk tcb0_clk = {
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.name = "tcb_clk",
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.name = "tcb0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
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.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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.type = CLK_TYPE_PERIPHERAL,
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};
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};
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@@ -192,6 +192,14 @@ static struct clk ohci_clk = {
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.parent = &uhphs_clk,
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.parent = &uhphs_clk,
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};
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};
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/* One additional fake clock for second TC block */
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static struct clk tcb1_clk = {
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.name = "tcb1_clk",
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.pmc_mask = 0,
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.type = CLK_TYPE_PERIPHERAL,
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.parent = &tcb0_clk,
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};
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static struct clk *periph_clocks[] __initdata = {
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioA_clk,
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&pioB_clk,
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&pioB_clk,
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@@ -208,7 +216,7 @@ static struct clk *periph_clocks[] __initdata = {
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&spi1_clk,
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&spi1_clk,
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&ssc0_clk,
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&ssc0_clk,
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&ssc1_clk,
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&ssc1_clk,
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&tcb_clk,
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&tcb0_clk,
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&pwm_clk,
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&pwm_clk,
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&tsc_clk,
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&tsc_clk,
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&dma_clk,
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&dma_clk,
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@@ -221,6 +229,7 @@ static struct clk *periph_clocks[] __initdata = {
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&mmc1_clk,
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&mmc1_clk,
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// irq0
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// irq0
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&ohci_clk,
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&ohci_clk,
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&tcb1_clk,
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};
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};
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/*
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/*
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@@ -835,9 +835,9 @@ static struct platform_device at91sam9g45_tcb1_device = {
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static void __init at91_add_device_tc(void)
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static void __init at91_add_device_tc(void)
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{
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{
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/* this chip has one clock and irq for all six TC channels */
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/* this chip has one clock and irq for all six TC channels */
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at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
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at91_clock_associate("tcb0_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
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platform_device_register(&at91sam9g45_tcb0_device);
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platform_device_register(&at91sam9g45_tcb0_device);
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at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
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at91_clock_associate("tcb1_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
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platform_device_register(&at91sam9g45_tcb1_device);
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platform_device_register(&at91sam9g45_tcb1_device);
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}
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}
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#else
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#else
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