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ARM: SMP: pass an ipi number to smp_cross_call()

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This allows us to use smp_cross_call() to trigger a number of different
software generated interrupts, rather than combining them all on one
SGI.  Recover the SGI number via do_IPI.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2010-11-15 09:42:08 +00:00
parent d92e04713c
commit ad3b6993b9
15 changed files with 24 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/include/asm/smp.h
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@@ -38,7 +38,7 @@ extern void show_ipi_list(struct seq_file *p);
/* /*
* Called from assembly code, this handles an IPI. * Called from assembly code, this handles an IPI.
*/ */
asmlinkage void do_IPI(struct pt_regs *regs); asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);
/* /*
* Setup the set of possible CPUs (via set_cpu_possible) * Setup the set of possible CPUs (via set_cpu_possible)
@@ -53,7 +53,7 @@ extern void smp_store_cpu_info(unsigned int cpuid);
/* /*
* Raise an IPI cross call on CPUs in callmap. * Raise an IPI cross call on CPUs in callmap.
*/ */
extern void smp_cross_call(const struct cpumask *mask); extern void smp_cross_call(const struct cpumask *mask, int ipi);
/* /*
* Boot a secondary CPU, and assign it the specified idle task. * Boot a secondary CPU, and assign it the specified idle task.

2
arch/arm/kernel/entry-armv.S
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@@ -48,7 +48,7 @@
*/ */
ALT_SMP(test_for_ipi r0, r6, r5, lr) ALT_SMP(test_for_ipi r0, r6, r5, lr)
ALT_UP_B(9997f) ALT_UP_B(9997f)
movne r0, sp movne r1, sp
adrne lr, BSYM(1b) adrne lr, BSYM(1b)
bne do_IPI bne do_IPI

10
arch/arm/kernel/smp.c
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@@ -404,7 +404,7 @@ static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg)
/* /*
* Call the platform specific cross-CPU call function. * Call the platform specific cross-CPU call function.
*/ */
smp_cross_call(mask); smp_cross_call(mask, 1);
local_irq_restore(flags); local_irq_restore(flags);
} }
@@ -537,14 +537,8 @@ static void ipi_cpu_stop(unsigned int cpu)
/* /*
* Main handler for inter-processor interrupts * Main handler for inter-processor interrupts
*
* For ARM, the ipimask now only identifies a single
* category of IPI (Bit 1 IPIs have been replaced by a
* different mechanism):
*
* Bit 0 - Inter-processor function call
*/ */
asmlinkage void __exception do_IPI(struct pt_regs *regs) asmlinkage void __exception do_IPI(int ipinr, struct pt_regs *regs)
{ {
unsigned int cpu = smp_processor_id(); unsigned int cpu = smp_processor_id();
struct ipi_data *ipi = &per_cpu(ipi_data, cpu); struct ipi_data *ipi = &per_cpu(ipi_data, cpu);

4
arch/arm/mach-msm/include/mach/smp.h
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@@ -31,9 +31,9 @@
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
static inline void smp_cross_call(const struct cpumask *mask) static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{ {
gic_raise_softirq(mask, 1); gic_raise_softirq(mask, ipi);
} }
#endif #endif

2
arch/arm/mach-omap2/omap-smp.c
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@@ -76,7 +76,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
omap_modify_auxcoreboot0(0x200, 0xfffffdff); omap_modify_auxcoreboot0(0x200, 0xfffffdff);
flush_cache_all(); flush_cache_all();
smp_wmb(); smp_wmb();
smp_cross_call(cpumask_of(cpu)); smp_cross_call(cpumask_of(cpu), 1);
/* /*
* Now the secondary core is starting up let it run its * Now the secondary core is starting up let it run its

4
arch/arm/mach-realview/include/mach/smp.h
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@@ -7,9 +7,9 @@
/* /*
* We use IRQ1 as the IPI * We use IRQ1 as the IPI
*/ */
static inline void smp_cross_call(const struct cpumask *mask) static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{ {
gic_raise_softirq(mask, 1); gic_raise_softirq(mask, ipi);
} }
#endif #endif

2
arch/arm/mach-realview/platsmp.c
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@@ -116,7 +116,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* Use smp_cross_call() for this, since there's little * Use smp_cross_call() for this, since there's little
* point duplicating the code here * point duplicating the code here
*/ */
smp_cross_call(cpumask_of(cpu)); smp_cross_call(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {

4
arch/arm/mach-s5pv310/include/mach/smp.h
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@@ -14,9 +14,9 @@ extern void __iomem *gic_cpu_base_addr;
/* /*
* We use IRQ1 as the IPI * We use IRQ1 as the IPI
*/ */
static inline void smp_cross_call(const struct cpumask *mask) static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{ {
gic_raise_softirq(mask, 1); gic_raise_softirq(mask, ipi);
} }
#endif #endif

2
arch/arm/mach-s5pv310/platsmp.c
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@@ -97,7 +97,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the boot monitor to read the system wide flags register, * the boot monitor to read the system wide flags register,
* and branch to the address found there. * and branch to the address found there.
*/ */
smp_cross_call(cpumask_of(cpu)); smp_cross_call(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {

4
arch/arm/mach-tegra/include/mach/smp.h
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@@ -7,9 +7,9 @@
/* /*
* We use IRQ1 as the IPI * We use IRQ1 as the IPI
*/ */
static inline void smp_cross_call(const struct cpumask *mask) static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{ {
gic_raise_softirq(mask, 1); gic_raise_softirq(mask, ipi);
} }
#endif #endif

4
arch/arm/mach-ux500/include/mach/smp.h
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@@ -18,8 +18,8 @@ extern void u8500_secondary_startup(void);
/* /*
* We use IRQ1 as the IPI * We use IRQ1 as the IPI
*/ */
static inline void smp_cross_call(const struct cpumask *mask) static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{ {
gic_raise_softirq(mask, 1); gic_raise_softirq(mask, ipi);
} }
#endif #endif

2
arch/arm/mach-ux500/platsmp.c
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@@ -78,7 +78,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
smp_cross_call(cpumask_of(cpu)); smp_cross_call(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {

4
arch/arm/mach-vexpress/include/mach/smp.h
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@@ -7,8 +7,8 @@
/* /*
* We use IRQ1 as the IPI * We use IRQ1 as the IPI
*/ */
static inline void smp_cross_call(const struct cpumask *mask) static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{ {
gic_raise_softirq(mask, 1); gic_raise_softirq(mask, ipi);
} }
#endif #endif

2
arch/arm/mach-vexpress/platsmp.c
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@@ -92,7 +92,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the boot monitor to read the system wide flags register, * the boot monitor to read the system wide flags register,
* and branch to the address found there. * and branch to the address found there.
*/ */
smp_cross_call(cpumask_of(cpu)); smp_cross_call(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {

4
arch/arm/plat-omap/include/plat/smp.h
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@@ -29,9 +29,9 @@ extern u32 omap_read_auxcoreboot0(void);
/* /*
* We use Soft IRQ1 as the IPI * We use Soft IRQ1 as the IPI
*/ */
static inline void smp_cross_call(const struct cpumask *mask) static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{ {
gic_raise_softirq(mask, 1); gic_raise_softirq(mask, ipi);
} }
#endif #endif