ACPICA: minimal patch to integrate new tables into Linux
Signed-off-by: Len Brown <len.brown@intel.com>
This commit is contained in:
committed by
Len Brown
parent
a4bbb810de
commit
ad71860a17
@@ -160,7 +160,7 @@ static inline u32 ticks_elapsed(u32 t1, u32 t2)
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{
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if (t2 >= t1)
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return (t2 - t1);
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else if (!acpi_fadt.tmr_val_ext)
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else if (!(acpi_fadt.flags & ACPI_FADT_32BIT_TIMER))
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return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
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else
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return ((0xFFFFFFFF - t1) + t2);
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@@ -236,7 +236,7 @@ static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
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/* Dummy wait op - must do something useless after P_LVL2 read
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because chipsets cannot guarantee that STPCLK# signal
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gets asserted in time to freeze execution properly. */
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unused = inl(acpi_fadt.xpm_tmr_blk.address);
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unused = inl(acpi_fadt.xpm_timer_block.address);
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}
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}
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@@ -338,7 +338,7 @@ static void acpi_processor_idle(void)
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* detection phase, to work cleanly with logical CPU hotplug.
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*/
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if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
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!pr->flags.has_cst && !acpi_fadt.plvl2_up)
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!pr->flags.has_cst && !(acpi_fadt.flags & ACPI_FADT_C2_MP_SUPPORTED))
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cx = &pr->power.states[ACPI_STATE_C1];
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#endif
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@@ -384,11 +384,11 @@ static void acpi_processor_idle(void)
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case ACPI_STATE_C2:
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/* Get start time (ticks) */
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t1 = inl(acpi_fadt.xpm_tmr_blk.address);
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t1 = inl(acpi_fadt.xpm_timer_block.address);
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/* Invoke C2 */
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acpi_cstate_enter(cx);
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/* Get end time (ticks) */
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t2 = inl(acpi_fadt.xpm_tmr_blk.address);
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t2 = inl(acpi_fadt.xpm_timer_block.address);
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#ifdef CONFIG_GENERIC_TIME
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/* TSC halts in C2, so notify users */
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@@ -420,11 +420,11 @@ static void acpi_processor_idle(void)
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}
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/* Get start time (ticks) */
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t1 = inl(acpi_fadt.xpm_tmr_blk.address);
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t1 = inl(acpi_fadt.xpm_timer_block.address);
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/* Invoke C3 */
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acpi_cstate_enter(cx);
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/* Get end time (ticks) */
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t2 = inl(acpi_fadt.xpm_tmr_blk.address);
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t2 = inl(acpi_fadt.xpm_timer_block.address);
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if (pr->flags.bm_check) {
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/* Enable bus master arbitration */
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atomic_dec(&c3_cpu_count);
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@@ -457,7 +457,7 @@ static void acpi_processor_idle(void)
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#ifdef CONFIG_HOTPLUG_CPU
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/* Don't do promotion/demotion */
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if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
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!pr->flags.has_cst && !acpi_fadt.plvl2_up) {
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!pr->flags.has_cst && !(acpi_fadt.flags & ACPI_FADT_C2_MP_SUPPORTED)) {
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next_state = cx;
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goto end;
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}
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@@ -627,7 +627,8 @@ static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
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* Check for P_LVL2_UP flag before entering C2 and above on
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* an SMP system.
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*/
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if ((num_online_cpus() > 1) && !acpi_fadt.plvl2_up)
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if ((num_online_cpus() > 1) &&
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!(acpi_fadt.flags & ACPI_FADT_C2_MP_SUPPORTED))
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return -ENODEV;
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#endif
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@@ -636,8 +637,8 @@ static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
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pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
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/* determine latencies from FADT */
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pr->power.states[ACPI_STATE_C2].latency = acpi_fadt.plvl2_lat;
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pr->power.states[ACPI_STATE_C3].latency = acpi_fadt.plvl3_lat;
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pr->power.states[ACPI_STATE_C2].latency = acpi_fadt.C2latency;
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pr->power.states[ACPI_STATE_C3].latency = acpi_fadt.C3latency;
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"lvl2[0x%08x] lvl3[0x%08x]\n",
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@@ -883,7 +884,7 @@ static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
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* WBINVD should be set in fadt, for C3 state to be
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* supported on when bm_check is not required.
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*/
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if (acpi_fadt.wb_invd != 1) {
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if (!(acpi_fadt.flags & ACPI_FADT_WBINVD)) {
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"Cache invalidation should work properly"
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" for C3 to be enabled on SMP systems\n"));
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@@ -1164,9 +1165,9 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
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if (!pr)
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return -EINVAL;
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if (acpi_fadt.cst_cnt && !nocst) {
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if (acpi_fadt.cst_control && !nocst) {
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status =
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acpi_os_write_port(acpi_fadt.smi_cmd, acpi_fadt.cst_cnt, 8);
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acpi_os_write_port(acpi_fadt.smi_command, acpi_fadt.cst_control, 8);
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if (ACPI_FAILURE(status)) {
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ACPI_EXCEPTION((AE_INFO, status,
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"Notifying BIOS of _CST ability failed"));
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