sh_eth: Add support of SH7763 to sh_eth
SH7763 has Ethernet core same as SH7710/SH7712. Positions of some registry are different, but the basic part is the same. I add support of ethernet of sh7763 to sh_eth. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Nobuhiro Iwamatsu
committed by
Jeff Garzik
Jeff Garzik
parent
d02a4e31ed
commit
b0ca2a21f7
@ -32,118 +32,249 @@
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#define CARDNAME "sh-eth"
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#define TX_TIMEOUT (5*HZ)
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#define TX_RING_SIZE 128 /* Tx ring size */
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#define RX_RING_SIZE 128 /* Rx ring size */
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#define RX_OFFSET 2 /* skb offset */
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#define TX_RING_SIZE 64 /* Tx ring size */
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#define RX_RING_SIZE 64 /* Rx ring size */
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#define ETHERSMALL 60
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#define PKT_BUF_SZ 1538
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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#define SH7763_SKB_ALIGN 32
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/* Chip Base Address */
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#define SH_TSU_ADDR 0xA7000804
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# define SH_TSU_ADDR 0xFFE01800
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# define ARSTR 0xFFE01800
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/* Chip Registers */
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/* E-DMAC */
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#define EDMR 0x0000
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#define EDTRR 0x0004
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#define EDRRR 0x0008
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#define TDLAR 0x000C
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#define RDLAR 0x0010
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#define EESR 0x0014
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#define EESIPR 0x0018
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#define TRSCER 0x001C
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#define RMFCR 0x0020
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#define TFTR 0x0024
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#define FDR 0x0028
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#define RMCR 0x002C
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#define EDOCR 0x0030
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#define FCFTR 0x0034
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#define RPADIR 0x0038
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#define TRIMD 0x003C
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#define RBWAR 0x0040
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#define RDFAR 0x0044
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#define TBRAR 0x004C
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#define TDFAR 0x0050
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/* Ether Register */
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#define ECMR 0x0160
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#define ECSR 0x0164
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#define ECSIPR 0x0168
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#define PIR 0x016C
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#define MAHR 0x0170
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#define MALR 0x0174
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#define RFLR 0x0178
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#define PSR 0x017C
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#define TROCR 0x0180
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#define CDCR 0x0184
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#define LCCR 0x0188
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#define CNDCR 0x018C
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#define CEFCR 0x0194
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#define FRECR 0x0198
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#define TSFRCR 0x019C
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#define TLFRCR 0x01A0
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#define RFCR 0x01A4
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#define MAFCR 0x01A8
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#define IPGR 0x01B4
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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#define APR 0x01B8
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#define MPR 0x01BC
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#define TPAUSER 0x1C4
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#define BCFR 0x1CC
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#endif /* CONFIG_CPU_SH7710 */
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# define EDSR 0x000
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# define EDMR 0x400
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# define EDTRR 0x408
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# define EDRRR 0x410
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# define EESR 0x428
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# define EESIPR 0x430
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# define TDLAR 0x010
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# define TDFAR 0x014
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# define TDFXR 0x018
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# define TDFFR 0x01C
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# define RDLAR 0x030
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# define RDFAR 0x034
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# define RDFXR 0x038
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# define RDFFR 0x03C
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# define TRSCER 0x438
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# define RMFCR 0x440
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# define TFTR 0x448
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# define FDR 0x450
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# define RMCR 0x458
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# define RPADIR 0x460
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# define FCFTR 0x468
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#define ARSTR 0x0800
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/* Ether Register */
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# define ECMR 0x500
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# define ECSR 0x510
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# define ECSIPR 0x518
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# define PIR 0x520
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# define PSR 0x528
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# define PIPR 0x52C
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# define RFLR 0x508
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# define APR 0x554
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# define MPR 0x558
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# define PFTCR 0x55C
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# define PFRCR 0x560
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# define TPAUSER 0x564
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# define GECMR 0x5B0
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# define BCULR 0x5B4
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# define MAHR 0x5C0
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# define MALR 0x5C8
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# define TROCR 0x700
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# define CDCR 0x708
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# define LCCR 0x710
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# define CEFCR 0x740
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# define FRECR 0x748
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# define TSFRCR 0x750
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# define TLFRCR 0x758
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# define RFCR 0x760
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# define CERCR 0x768
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# define CEECR 0x770
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# define MAFCR 0x778
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/* TSU Absolute Address */
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# define TSU_CTRST 0x004
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# define TSU_FWEN0 0x010
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# define TSU_FWEN1 0x014
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# define TSU_FCM 0x18
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# define TSU_BSYSL0 0x20
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# define TSU_BSYSL1 0x24
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# define TSU_PRISL0 0x28
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# define TSU_PRISL1 0x2C
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# define TSU_FWSL0 0x30
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# define TSU_FWSL1 0x34
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# define TSU_FWSLC 0x38
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# define TSU_QTAG0 0x40
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# define TSU_QTAG1 0x44
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# define TSU_FWSR 0x50
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# define TSU_FWINMK 0x54
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# define TSU_ADQT0 0x48
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# define TSU_ADQT1 0x4C
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# define TSU_VTAG0 0x58
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# define TSU_VTAG1 0x5C
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# define TSU_ADSBSY 0x60
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# define TSU_TEN 0x64
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# define TSU_POST1 0x70
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# define TSU_POST2 0x74
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# define TSU_POST3 0x78
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# define TSU_POST4 0x7C
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# define TSU_ADRH0 0x100
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# define TSU_ADRL0 0x104
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# define TSU_ADRH31 0x1F8
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# define TSU_ADRL31 0x1FC
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# define TXNLCR0 0x80
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# define TXALCR0 0x84
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# define RXNLCR0 0x88
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# define RXALCR0 0x8C
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# define FWNLCR0 0x90
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# define FWALCR0 0x94
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# define TXNLCR1 0xA0
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# define TXALCR1 0xA4
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# define RXNLCR1 0xA8
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# define RXALCR1 0xAC
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# define FWNLCR1 0xB0
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# define FWALCR1 0x40
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#else /* CONFIG_CPU_SUBTYPE_SH7763 */
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# define RX_OFFSET 2 /* skb offset */
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/* Chip base address */
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# define SH_TSU_ADDR 0xA7000804
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# define ARSTR 0xA7000800
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/* Chip Registers */
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/* E-DMAC */
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# define EDMR 0x0000
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# define EDTRR 0x0004
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# define EDRRR 0x0008
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# define TDLAR 0x000C
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# define RDLAR 0x0010
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# define EESR 0x0014
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# define EESIPR 0x0018
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# define TRSCER 0x001C
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# define RMFCR 0x0020
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# define TFTR 0x0024
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# define FDR 0x0028
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# define RMCR 0x002C
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# define EDOCR 0x0030
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# define FCFTR 0x0034
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# define RPADIR 0x0038
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# define TRIMD 0x003C
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# define RBWAR 0x0040
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# define RDFAR 0x0044
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# define TBRAR 0x004C
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# define TDFAR 0x0050
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/* Ether Register */
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# define ECMR 0x0160
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# define ECSR 0x0164
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# define ECSIPR 0x0168
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# define PIR 0x016C
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# define MAHR 0x0170
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# define MALR 0x0174
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# define RFLR 0x0178
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# define PSR 0x017C
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# define TROCR 0x0180
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# define CDCR 0x0184
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# define LCCR 0x0188
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# define CNDCR 0x018C
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# define CEFCR 0x0194
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# define FRECR 0x0198
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# define TSFRCR 0x019C
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# define TLFRCR 0x01A0
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# define RFCR 0x01A4
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# define MAFCR 0x01A8
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# define IPGR 0x01B4
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# if defined(CONFIG_CPU_SUBTYPE_SH7710)
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# define APR 0x01B8
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# define MPR 0x01BC
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# define TPAUSER 0x1C4
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# define BCFR 0x1CC
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# endif /* CONFIG_CPU_SH7710 */
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/* TSU */
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#define TSU_CTRST 0x004
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#define TSU_FWEN0 0x010
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#define TSU_FWEN1 0x014
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#define TSU_FCM 0x018
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#define TSU_BSYSL0 0x020
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#define TSU_BSYSL1 0x024
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#define TSU_PRISL0 0x028
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#define TSU_PRISL1 0x02C
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#define TSU_FWSL0 0x030
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#define TSU_FWSL1 0x034
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#define TSU_FWSLC 0x038
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#define TSU_QTAGM0 0x040
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#define TSU_QTAGM1 0x044
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#define TSU_ADQT0 0x048
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#define TSU_ADQT1 0x04C
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#define TSU_FWSR 0x050
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#define TSU_FWINMK 0x054
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#define TSU_ADSBSY 0x060
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#define TSU_TEN 0x064
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#define TSU_POST1 0x070
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#define TSU_POST2 0x074
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#define TSU_POST3 0x078
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#define TSU_POST4 0x07C
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#define TXNLCR0 0x080
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#define TXALCR0 0x084
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#define RXNLCR0 0x088
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#define RXALCR0 0x08C
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#define FWNLCR0 0x090
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#define FWALCR0 0x094
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#define TXNLCR1 0x0A0
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#define TXALCR1 0x0A4
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#define RXNLCR1 0x0A8
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#define RXALCR1 0x0AC
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#define FWNLCR1 0x0B0
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#define FWALCR1 0x0B4
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# define TSU_CTRST 0x004
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# define TSU_FWEN0 0x010
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# define TSU_FWEN1 0x014
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# define TSU_FCM 0x018
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# define TSU_BSYSL0 0x020
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# define TSU_BSYSL1 0x024
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# define TSU_PRISL0 0x028
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# define TSU_PRISL1 0x02C
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# define TSU_FWSL0 0x030
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# define TSU_FWSL1 0x034
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# define TSU_FWSLC 0x038
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# define TSU_QTAGM0 0x040
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# define TSU_QTAGM1 0x044
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# define TSU_ADQT0 0x048
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# define TSU_ADQT1 0x04C
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# define TSU_FWSR 0x050
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# define TSU_FWINMK 0x054
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# define TSU_ADSBSY 0x060
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# define TSU_TEN 0x064
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# define TSU_POST1 0x070
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# define TSU_POST2 0x074
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# define TSU_POST3 0x078
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# define TSU_POST4 0x07C
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# define TXNLCR0 0x080
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# define TXALCR0 0x084
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# define RXNLCR0 0x088
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# define RXALCR0 0x08C
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# define FWNLCR0 0x090
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# define FWALCR0 0x094
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# define TXNLCR1 0x0A0
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# define TXALCR1 0x0A4
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# define RXNLCR1 0x0A8
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# define RXALCR1 0x0AC
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# define FWNLCR1 0x0B0
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# define FWALCR1 0x0B4
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#define TSU_ADRH0 0x0100
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#define TSU_ADRL0 0x0104
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#define TSU_ADRL31 0x01FC
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/* Register's bits */
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#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
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/*
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* Register's bits
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*/
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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/* EDSR */
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enum EDSR_BIT {
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EDSR_ENT = 0x01, EDSR_ENR = 0x02,
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};
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#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
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/* GECMR */
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enum GECMR_BIT {
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GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
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};
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#endif
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/* EDMR */
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enum DMAC_M_BIT {
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, EDMR_SRST = 0x01,
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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EDMR_SRST = 0x03,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#else /* CONFIG_CPU_SUBTYPE_SH7763 */
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EDMR_SRST = 0x01,
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#endif
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};
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/* EDTRR */
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enum DMAC_T_BIT {
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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EDTRR_TRNS = 0x03,
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#else
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EDTRR_TRNS = 0x01,
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#endif
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};
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/* EDRRR*/
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@ -173,21 +304,47 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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/* EESR */
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enum EESR_BIT {
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EESR_TWB = 0x40000000, EESR_TABT = 0x04000000,
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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EESR_TWB = 0x40000000,
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#else
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EESR_TWB = 0xC0000000,
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EESR_TC1 = 0x20000000,
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EESR_TUC = 0x10000000,
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EESR_ROC = 0x80000000,
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#endif
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EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
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EESR_ADE = 0x00800000, EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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EESR_TINT4 = 0x00000800, EESR_TINT3 = 0x00000400,
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EESR_TINT2 = 0x00000200, EESR_TINT1 = 0x00000100,
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EESR_RINT8 = 0x00000080, EESR_RINT5 = 0x00000010,
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EESR_RINT4 = 0x00000008, EESR_RINT3 = 0x00000004,
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EESR_RINT2 = 0x00000002, EESR_RINT1 = 0x00000001,
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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EESR_ADE = 0x00800000,
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#endif
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EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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EESR_CND = 0x00000800,
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#endif
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EESR_DLC = 0x00000400,
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EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
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EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
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EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
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EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
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EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
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};
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#define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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# define TX_CHECK (EESR_TC1 | EESR_FTC)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
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#else
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# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
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#endif
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/* EESIPR */
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enum DMAC_IM_BIT {
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@ -207,8 +364,8 @@ enum DMAC_IM_BIT {
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/* Receive descriptor bit */
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enum RD_STS_BIT {
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RD_RACT = 0x80000000, RC_RDEL = 0x40000000,
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RC_RFP1 = 0x20000000, RC_RFP0 = 0x10000000,
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RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
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RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
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RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
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RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
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RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
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@ -216,9 +373,9 @@ enum RD_STS_BIT {
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RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
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RD_RFS1 = 0x00000001,
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};
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#define RDF1ST RC_RFP1
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#define RDFEND RC_RFP0
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#define RD_RFP (RC_RFP1|RC_RFP0)
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#define RDF1ST RD_RFP1
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#define RDFEND RD_RFP0
|
||||
#define RD_RFP (RD_RFP1|RD_RFP0)
|
||||
|
||||
/* FCFTR */
|
||||
enum FCFTR_BIT {
|
||||
@ -231,7 +388,8 @@ enum FCFTR_BIT {
|
||||
|
||||
/* Transfer descriptor bit */
|
||||
enum TD_STS_BIT {
|
||||
TD_TACT = 0x80000000, TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
|
||||
TD_TACT = 0x80000000,
|
||||
TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
|
||||
TD_TFP0 = 0x10000000,
|
||||
};
|
||||
#define TDF1ST TD_TFP1
|
||||
@ -242,6 +400,10 @@ enum TD_STS_BIT {
|
||||
enum RECV_RST_BIT { RMCR_RST = 0x01, };
|
||||
/* ECMR */
|
||||
enum FELIC_MODE_BIT {
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7763
|
||||
ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
|
||||
ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
|
||||
#endif
|
||||
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
|
||||
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
|
||||
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
|
||||
@ -249,18 +411,45 @@ enum FELIC_MODE_BIT {
|
||||
ECMR_PRM = 0x00000001,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7763
|
||||
#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\
|
||||
ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
|
||||
#else
|
||||
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
|
||||
#endif
|
||||
|
||||
/* ECSR */
|
||||
enum ECSR_STATUS_BIT {
|
||||
ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, ECSR_LCHNG = 0x04,
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7763
|
||||
ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
|
||||
#endif
|
||||
ECSR_LCHNG = 0x04,
|
||||
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7763
|
||||
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
|
||||
#else
|
||||
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
|
||||
ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
|
||||
#endif
|
||||
|
||||
/* ECSIPR */
|
||||
enum ECSIPR_STATUS_MASK_BIT {
|
||||
ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, ECSIPR_LCHNGIP = 0x04,
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7763
|
||||
ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
|
||||
#endif
|
||||
ECSIPR_LCHNGIP = 0x04,
|
||||
ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7763
|
||||
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
|
||||
#else
|
||||
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
|
||||
ECSIPR_ICDIP | ECSIPR_MPDIP)
|
||||
#endif
|
||||
|
||||
/* APR */
|
||||
enum APR_BIT {
|
||||
APR_AP = 0x00000001,
|
||||
@ -285,6 +474,15 @@ enum RPADIR_BIT {
|
||||
RPADIR_PADR = 0x0003f,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
# define RPADIR_INIT (0x00)
|
||||
#else
|
||||
# define RPADIR_INIT (RPADIR_PADS1)
|
||||
#endif
|
||||
|
||||
/* RFLR */
|
||||
#define RFLR_VALUE 0x1000
|
||||
|
||||
/* FDR */
|
||||
enum FIFO_SIZE_BIT {
|
||||
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
|
||||
@ -316,7 +514,7 @@ enum PHY_ANA_BIT {
|
||||
PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
|
||||
PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
|
||||
PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
|
||||
PHY_A_SEL = 0x001f,
|
||||
PHY_A_SEL = 0x001e,
|
||||
};
|
||||
/* PHY_ANL */
|
||||
enum PHY_ANL_BIT {
|
||||
@ -449,6 +647,10 @@ struct sh_eth_private {
|
||||
struct net_device_stats tsu_stats; /* TSU forward status */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7763
|
||||
/* SH7763 has endian control register */
|
||||
#define swaps(x, y)
|
||||
#else
|
||||
static void swaps(char *src, int len)
|
||||
{
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
@ -460,5 +662,5 @@ static void swaps(char *src, int len)
|
||||
*p = swab32(*p);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user