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[PATCH] defxx: Big-endian hosts support

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The PDQ DMA engine requires a different byte-swapping mode for big-endian
hosts; also the MAC address which is read from a register through PIO has
to be byte-swapped.  These changes have been verified with DEFPA-DC (PCI)
boards and a Broadcom BCM91250A (MIPS CPU based) host.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Maciej W. Rozycki
2006-10-23 13:53:17 +01:00
committed by Jeff Garzik
parent c3a9392e4f
commit b2e68aa337
2 changed files with 31 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/net/defxx.c
View File

@@ -192,6 +192,7 @@
* 04 Aug 2003 macro Converted to the DMA API. * 04 Aug 2003 macro Converted to the DMA API.
* 14 Aug 2004 macro Fix device names reported. * 14 Aug 2004 macro Fix device names reported.
* 14 Jun 2005 macro Use irqreturn_t. * 14 Jun 2005 macro Use irqreturn_t.
* 23 Oct 2006 macro Big-endian host support.
*/ */
/* Include files */ /* Include files */
@@ -218,8 +219,8 @@
/* Version information string should be updated prior to each new release! */ /* Version information string should be updated prior to each new release! */
#define DRV_NAME "defxx" #define DRV_NAME "defxx"
#define DRV_VERSION "v1.08" #define DRV_VERSION "v1.09"
#define DRV_RELDATE "2005/06/14" #define DRV_RELDATE "2006/10/23"
static char version[] __devinitdata = static char version[] __devinitdata =
DRV_NAME ": " DRV_VERSION " " DRV_RELDATE DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
@@ -859,6 +860,7 @@ static int __devinit dfx_driver_init(struct net_device *dev,
print_name); print_name);
return(DFX_K_FAILURE); return(DFX_K_FAILURE);
} }
data = cpu_to_le32(data);
memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32)); memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
@@ -867,6 +869,7 @@ static int __devinit dfx_driver_init(struct net_device *dev,
print_name); print_name);
return(DFX_K_FAILURE); return(DFX_K_FAILURE);
} }
data = cpu_to_le32(data);
memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16)); memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
/* /*
@@ -1085,27 +1088,23 @@ static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
} }
/* /*
* Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state * Set the base address of Descriptor Block and bring adapter
* to DMA_AVAILABLE state.
* *
* Note: We also set the literal and data swapping requirements in this * Note: We also set the literal and data swapping requirements
* command. Since this driver presently runs on Intel platforms * in this command.
* which are Little Endian, we'll tell the adapter to byte swap
* data only. This code will need to change when we support
* Big Endian systems (eg. PowerPC).
* *
* Assumption: 32-bit physical address of descriptor block is 8Kbyte * Assumption: 32-bit physical address of descriptor block
* aligned. That is, bits 0-12 of the address must be zero. * is 8Kbyte aligned.
*/ */
if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
if (dfx_hw_port_ctrl_req(bp, (u32)(bp->descr_block_phys |
PI_PCTRL_M_INIT, PI_PDATA_A_INIT_M_BSWAP_INIT),
(u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA), 0, NULL) != DFX_K_SUCCESS) {
0, printk("%s: Could not set descriptor block address!\n",
NULL) != DFX_K_SUCCESS) bp->dev->name);
{ return DFX_K_FAILURE;
printk("%s: Could not set descriptor block address!\n", bp->dev->name); }
return(DFX_K_FAILURE);
}
/* Set transmit flush timeout value */ /* Set transmit flush timeout value */

15
drivers/net/defxx.h
View File

@@ -25,6 +25,7 @@
* macros to DEFXX.C. * macros to DEFXX.C.
* 12-Sep-96 LVS Removed packet request header pointers. * 12-Sep-96 LVS Removed packet request header pointers.
* 04 Aug 2003 macro Converted to the DMA API. * 04 Aug 2003 macro Converted to the DMA API.
* 23 Oct 2006 macro Big-endian host support.
*/ */
#ifndef _DEFXX_H_ #ifndef _DEFXX_H_
@@ -1344,7 +1345,7 @@ typedef struct
/* Register definition structures are defined for both big and little endian systems */ /* Register definition structures are defined for both big and little endian systems */
#ifndef BIG_ENDIAN #ifndef __BIG_ENDIAN
/* Little endian format of Type 1 Producer register */ /* Little endian format of Type 1 Producer register */
@@ -1402,7 +1403,11 @@ typedef union
} index; } index;
} PI_TYPE_2_CONSUMER; } PI_TYPE_2_CONSUMER;
#else /* Define swapping required by DMA transfers. */
#define PI_PDATA_A_INIT_M_BSWAP_INIT \
(PI_PDATA_A_INIT_M_BSWAP_DATA)
#else /* __BIG_ENDIAN */
/* Big endian format of Type 1 Producer register */ /* Big endian format of Type 1 Producer register */
@@ -1460,7 +1465,11 @@ typedef union
} index; } index;
} PI_TYPE_2_CONSUMER; } PI_TYPE_2_CONSUMER;
#endif /* #ifndef BIG_ENDIAN */ /* Define swapping required by DMA transfers. */
#define PI_PDATA_A_INIT_M_BSWAP_INIT \
(PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
#endif /* __BIG_ENDIAN */
/* Define EISA controller register offsets */ /* Define EISA controller register offsets */