[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL bit. MPU PLL is driven by 512*CLK32 for each case. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@@ -102,7 +102,7 @@ EXPORT_SYMBOL(imx_gpio_mode);
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* f = 2 * f_ref * --------------------
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* pd + 1
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*/
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static unsigned int imx_decode_pll(unsigned int pll)
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static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref)
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{
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unsigned long long ll;
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unsigned long quot;
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@@ -111,7 +111,6 @@ static unsigned int imx_decode_pll(unsigned int pll)
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u32 mfn = pll & 0x3ff;
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u32 mfd = (pll >> 16) & 0x3ff;
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u32 pd = (pll >> 26) & 0xf;
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u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
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mfi = mfi <= 5 ? 5 : mfi;
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@@ -124,13 +123,15 @@ static unsigned int imx_decode_pll(unsigned int pll)
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unsigned int imx_get_system_clk(void)
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{
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return imx_decode_pll(SPCTL0);
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u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
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return imx_decode_pll(SPCTL0, f_ref);
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}
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EXPORT_SYMBOL(imx_get_system_clk);
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unsigned int imx_get_mcu_clk(void)
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{
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return imx_decode_pll(MPCTL0);
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return imx_decode_pll(MPCTL0, CLK32 * 512);
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}
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EXPORT_SYMBOL(imx_get_mcu_clk);
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