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sh: switch sh7724 to clkdev

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This patch converts the remaining sh7724 clocks
to use clkdev for lookup. The now unused name
and id from struct clk are also removed.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
2010-05-11 09:35:19 +00:00
committed by Paul Mundt
parent 53041f020b
commit b3f9f630d3
1 changed files with 7 additions and 10 deletions
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17
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
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@@ -41,8 +41,6 @@
/* Fixed 32 KHz root clock for RTC and Power Management purposes */ /* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = { static struct clk r_clk = {
.name = "rclk",
.id = -1,
.rate = 32768, .rate = 32768,
}; };
@@ -51,8 +49,6 @@ static struct clk r_clk = {
* from the platform code. * from the platform code.
*/ */
struct clk extal_clk = { struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333, .rate = 33333333,
}; };
@@ -76,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
}; };
static struct clk fll_clk = { static struct clk fll_clk = {
.name = "fll_clk",
.id = -1,
.ops = &fll_clk_ops, .ops = &fll_clk_ops,
.parent = &r_clk, .parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT, .flags = CLK_ENABLE_ON_INIT,
@@ -98,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
}; };
static struct clk pll_clk = { static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops, .ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT, .flags = CLK_ENABLE_ON_INIT,
}; };
@@ -115,8 +107,6 @@ static struct clk_ops div3_clk_ops = {
}; };
static struct clk div3_clk = { static struct clk div3_clk = {
.name = "div3_clk",
.id = -1,
.ops = &div3_clk_ops, .ops = &div3_clk_ops,
.parent = &pll_clk, .parent = &pll_clk,
}; };
@@ -234,6 +224,13 @@ static struct clk mstp_clks[HWBLK_NR] = {
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = { static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("fll_clk", &fll_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
CLKDEV_CON_ID("div3_clk", &div3_clk),
/* DIV4 clocks */ /* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),