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MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle
2008-10-11 16:18:53 +01:00
parent 60724ca59e
commit b65a75b8c9
1 changed files with 24 additions and 11 deletions
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35
arch/mips/lib/csum_partial.S
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@@ -270,13 +270,20 @@ LEAF(csum_partial)
#endif #endif
/* odd buffer alignment? */ /* odd buffer alignment? */
beqz t7, 1f #ifdef CPU_MIPSR2
nop wsbh v1, sum
sll v1, sum, 8 movn sum, v1, t7
#else
beqz t7, 1f /* odd buffer alignment? */
lui v1, 0x00ff
addu v1, 0x00ff
and t0, sum, v1
sll t0, t0, 8
srl sum, sum, 8 srl sum, sum, 8
or sum, v1 and sum, sum, v1
andi sum, 0xffff or sum, sum, t0
1: 1:
#endif
.set reorder .set reorder
/* Add the passed partial csum. */ /* Add the passed partial csum. */
ADDC32(sum, a2) ADDC32(sum, a2)
@@ -663,14 +670,20 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
addu sum, v1 addu sum, v1
#endif #endif
/* odd buffer alignment? */ #ifdef CPU_MIPSR2
beqz odd, 1f wsbh v1, sum
nop movn sum, v1, odd
sll v1, sum, 8 #else
beqz odd, 1f /* odd buffer alignment? */
lui v1, 0x00ff
addu v1, 0x00ff
and t0, sum, v1
sll t0, t0, 8
srl sum, sum, 8 srl sum, sum, 8
or sum, v1 and sum, sum, v1
andi sum, 0xffff or sum, sum, t0
1: 1:
#endif
.set reorder .set reorder
ADDC32(sum, psum) ADDC32(sum, psum)
jr ra jr ra