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[XTENSA] Flush the page-address in update-mmu instead of user-address

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The TLB entry for the user address doesn't exist at the time we
want to flush the caches, so use the page address. Note that processor
configurations with cache-aliasing issues are treated separately.

Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Chris Zankel
2007-09-06 01:38:18 -07:00
parent 49883224f6
commit b67360db14
1 changed files with 3 additions and 3 deletions
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6
arch/xtensa/mm/cache.c
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@@ -180,9 +180,9 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte)
#else #else
if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags) if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
&& (vma->vm_flags & VM_EXEC) != 0) { && (vma->vm_flags & VM_EXEC) != 0) {
unsigned long vaddr = addr & PAGE_MASK; unsigned long paddr = (unsigned long) page_address(page);
__flush_dcache_page(vaddr); __flush_dcache_page(paddr);
__invalidate_icache_page(vaddr); __invalidate_icache_page(paddr);
set_bit(PG_arch_1, &page->flags); set_bit(PG_arch_1, &page->flags);
} }
#endif #endif