Merge branch 'sh/for-2.6.27' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* 'sh/for-2.6.27' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: i2c: fix i2c-sh_mobile timing issues sh64: resume_kernel fix for kernel oops built with CONFIG_BKL_PREEMPT=y. sh: resume_kernel fix for kernel oops built with CONFIG_BKL_PREEMPT=y. sh: fix semtimedop syscall sh: update AP325RXA defconfig sh: update Migo-R defconfig sh: fix platform_resource_setup_memory() section mismatch sh: fix kexec entry point for crash kernels sh: crash kernel resource fix sh: fix ptrace_64.c:user_disable_single_step() sh64: re-add the __strnlen_user() prototype
This commit is contained in:
@@ -31,13 +31,84 @@
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#include <linux/clk.h>
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#include <linux/io.h>
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/* Transmit operation: */
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/* */
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/* 0 byte transmit */
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/* BUS: S A8 ACK P */
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/* IRQ: DTE WAIT */
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/* ICIC: */
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/* ICCR: 0x94 0x90 */
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/* ICDR: A8 */
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/* */
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/* 1 byte transmit */
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/* BUS: S A8 ACK D8(1) ACK P */
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/* IRQ: DTE WAIT WAIT */
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/* ICIC: -DTE */
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/* ICCR: 0x94 0x90 */
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/* ICDR: A8 D8(1) */
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/* */
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/* 2 byte transmit */
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/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */
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/* IRQ: DTE WAIT WAIT WAIT */
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/* ICIC: -DTE */
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/* ICCR: 0x94 0x90 */
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/* ICDR: A8 D8(1) D8(2) */
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/* */
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/* 3 bytes or more, +---------+ gets repeated */
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/* */
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/* */
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/* Receive operation: */
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/* */
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/* 0 byte receive - not supported since slave may hold SDA low */
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/* */
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/* 1 byte receive [TX] | [RX] */
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/* BUS: S A8 ACK | D8(1) ACK P */
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/* IRQ: DTE WAIT | WAIT DTE */
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/* ICIC: -DTE | +DTE */
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/* ICCR: 0x94 0x81 | 0xc0 */
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/* ICDR: A8 | D8(1) */
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/* */
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/* 2 byte receive [TX]| [RX] */
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/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */
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/* IRQ: DTE WAIT | WAIT WAIT DTE */
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/* ICIC: -DTE | +DTE */
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/* ICCR: 0x94 0x81 | 0xc0 */
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/* ICDR: A8 | D8(1) D8(2) */
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/* */
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/* 3 byte receive [TX] | [RX] */
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/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
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/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
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/* ICIC: -DTE | +DTE */
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/* ICCR: 0x94 0x81 | 0xc0 */
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/* ICDR: A8 | D8(1) D8(2) D8(3) */
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/* */
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/* 4 bytes or more, this part is repeated +---------+ */
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/* */
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/* */
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/* Interrupt order and BUSY flag */
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/* ___ _ */
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/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
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/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
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/* */
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/* S D7 D6 D5 D4 D3 D2 D1 D0 P */
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/* ___ */
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/* WAIT IRQ ________________________________/ \___________ */
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/* TACK IRQ ____________________________________/ \_______ */
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/* DTE IRQ __________________________________________/ \_ */
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/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
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/* _______________________________________________ */
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/* BUSY __/ \_ */
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/* */
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enum sh_mobile_i2c_op {
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OP_START = 0,
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OP_TX_ONLY,
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OP_TX_FIRST,
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OP_TX,
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OP_TX_STOP,
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OP_TX_TO_RX,
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OP_RX_ONLY,
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OP_RX,
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OP_RX_STOP,
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OP_RX_STOP_DATA,
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};
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struct sh_mobile_i2c_data {
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@@ -127,25 +198,34 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
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spin_lock_irqsave(&pd->lock, flags);
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switch (op) {
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case OP_START:
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case OP_START: /* issue start and trigger DTE interrupt */
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iowrite8(0x94, ICCR(pd));
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break;
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case OP_TX_ONLY:
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case OP_TX_FIRST: /* disable DTE interrupt and write data */
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iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
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iowrite8(data, ICDR(pd));
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break;
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case OP_TX_STOP:
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case OP_TX: /* write data */
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iowrite8(data, ICDR(pd));
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break;
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case OP_TX_STOP: /* write data and issue a stop afterwards */
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iowrite8(data, ICDR(pd));
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iowrite8(0x90, ICCR(pd));
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iowrite8(ICIC_ALE | ICIC_TACKE, ICIC(pd));
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break;
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case OP_TX_TO_RX:
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iowrite8(data, ICDR(pd));
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case OP_TX_TO_RX: /* select read mode */
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iowrite8(0x81, ICCR(pd));
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break;
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case OP_RX_ONLY:
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case OP_RX: /* just read data */
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ret = ioread8(ICDR(pd));
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break;
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case OP_RX_STOP:
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case OP_RX_STOP: /* enable DTE interrupt, issue stop */
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iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
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ICIC(pd));
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iowrite8(0xc0, ICCR(pd));
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break;
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case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
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iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
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ICIC(pd));
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ret = ioread8(ICDR(pd));
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iowrite8(0xc0, ICCR(pd));
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break;
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@@ -157,58 +237,120 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
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return ret;
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}
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static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
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{
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if (pd->pos == -1)
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return 1;
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return 0;
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}
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static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
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{
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if (pd->pos == (pd->msg->len - 1))
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return 1;
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return 0;
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}
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static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
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unsigned char *buf)
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{
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switch (pd->pos) {
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case -1:
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*buf = (pd->msg->addr & 0x7f) << 1;
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*buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
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break;
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default:
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*buf = pd->msg->buf[pd->pos];
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}
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}
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static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
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{
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unsigned char data;
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if (pd->pos == pd->msg->len)
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return 1;
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sh_mobile_i2c_get_data(pd, &data);
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if (sh_mobile_i2c_is_last_byte(pd))
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i2c_op(pd, OP_TX_STOP, data);
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else if (sh_mobile_i2c_is_first_byte(pd))
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i2c_op(pd, OP_TX_FIRST, data);
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else
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i2c_op(pd, OP_TX, data);
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pd->pos++;
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return 0;
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}
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static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
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{
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unsigned char data;
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int real_pos;
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do {
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if (pd->pos <= -1) {
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sh_mobile_i2c_get_data(pd, &data);
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if (sh_mobile_i2c_is_first_byte(pd))
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i2c_op(pd, OP_TX_FIRST, data);
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else
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i2c_op(pd, OP_TX, data);
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break;
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}
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if (pd->pos == 0) {
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i2c_op(pd, OP_TX_TO_RX, 0);
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break;
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}
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real_pos = pd->pos - 2;
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if (pd->pos == pd->msg->len) {
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if (real_pos < 0) {
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i2c_op(pd, OP_RX_STOP, 0);
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break;
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}
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data = i2c_op(pd, OP_RX_STOP_DATA, 0);
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} else
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data = i2c_op(pd, OP_RX, 0);
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pd->msg->buf[real_pos] = data;
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} while (0);
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pd->pos++;
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return pd->pos == (pd->msg->len + 2);
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}
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static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
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{
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struct platform_device *dev = dev_id;
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struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
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struct i2c_msg *msg = pd->msg;
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unsigned char data, sr;
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int wakeup = 0;
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unsigned char sr;
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int wakeup;
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sr = ioread8(ICSR(pd));
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pd->sr |= sr;
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pd->sr |= sr; /* remember state */
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dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
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(msg->flags & I2C_M_RD) ? "read" : "write",
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pd->pos, msg->len);
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(pd->msg->flags & I2C_M_RD) ? "read" : "write",
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pd->pos, pd->msg->len);
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if (sr & (ICSR_AL | ICSR_TACK)) {
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iowrite8(0, ICIC(pd)); /* disable interrupts */
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wakeup = 1;
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goto do_wakeup;
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}
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/* don't interrupt transaction - continue to issue stop */
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iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
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wakeup = 0;
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} else if (pd->msg->flags & I2C_M_RD)
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wakeup = sh_mobile_i2c_isr_rx(pd);
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else
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wakeup = sh_mobile_i2c_isr_tx(pd);
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if (pd->pos == msg->len) {
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i2c_op(pd, OP_RX_ONLY, 0);
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wakeup = 1;
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goto do_wakeup;
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}
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if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
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iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
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if (pd->pos == -1) {
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data = (msg->addr & 0x7f) << 1;
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data |= (msg->flags & I2C_M_RD) ? 1 : 0;
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} else
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data = msg->buf[pd->pos];
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if ((pd->pos == -1) || !(msg->flags & I2C_M_RD)) {
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if (msg->flags & I2C_M_RD)
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i2c_op(pd, OP_TX_TO_RX, data);
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else if (pd->pos == (msg->len - 1)) {
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i2c_op(pd, OP_TX_STOP, data);
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wakeup = 1;
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} else
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i2c_op(pd, OP_TX_ONLY, data);
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} else {
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if (pd->pos == (msg->len - 1))
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data = i2c_op(pd, OP_RX_STOP, 0);
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else
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data = i2c_op(pd, OP_RX_ONLY, 0);
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msg->buf[pd->pos] = data;
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}
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pd->pos++;
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do_wakeup:
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if (wakeup) {
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pd->sr |= SW_DONE;
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wake_up(&pd->wait);
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@@ -219,6 +361,11 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
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static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
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{
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if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
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dev_err(pd->dev, "Unsupported zero length i2c read\n");
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return -EIO;
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}
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/* Initialize channel registers */
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iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
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@@ -233,9 +380,8 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
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pd->pos = -1;
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pd->sr = 0;
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/* Enable all interrupts except wait */
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iowrite8(ioread8(ICIC(pd)) | ICIC_ALE | ICIC_TACKE | ICIC_DTEE,
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ICIC(pd));
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/* Enable all interrupts to begin with */
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iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
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return 0;
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}
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@@ -268,25 +414,18 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
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if (!k)
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dev_err(pd->dev, "Transfer request timed out\n");
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retry_count = 10;
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retry_count = 1000;
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again:
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val = ioread8(ICSR(pd));
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dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
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if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
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err = -EIO;
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break;
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}
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/* the interrupt handler may wake us up before the
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* transfer is finished, so poll the hardware
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* until we're done.
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*/
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if (!(!(val & ICSR_BUSY) && (val & ICSR_SCLM) &&
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(val & ICSR_SDAM))) {
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msleep(1);
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if (val & ICSR_BUSY) {
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udelay(10);
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if (retry_count--)
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goto again;
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@@ -294,6 +433,12 @@ again:
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dev_err(pd->dev, "Polling timed out\n");
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break;
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}
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/* handle missing acknowledge and arbitration lost */
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if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
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err = -EIO;
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break;
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}
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}
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deactivate_ch(pd);
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