ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30
Currently the tegra20 and tegra30 share the same symbol for tegra_clk_32k_ops. This will cause a compile error when building a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and modify tegra30_clk_32k_ops for tegra30. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren
parent
1dfacc1613
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b78c030ceb
@@ -231,6 +231,16 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
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return divider_u16 - 1;
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return divider_u16 - 1;
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}
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}
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static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return to_clk_tegra(hw)->fixed_rate;
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}
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struct clk_ops tegra_clk_32k_ops = {
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.recalc_rate = tegra_clk_fixed_recalc_rate,
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};
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/* clk_m functions */
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/* clk_m functions */
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static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
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static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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unsigned long prate)
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@@ -478,7 +478,7 @@ static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
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return to_clk_tegra(hw)->fixed_rate;
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return to_clk_tegra(hw)->fixed_rate;
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}
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}
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struct clk_ops tegra_clk_32k_ops = {
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struct clk_ops tegra30_clk_32k_ops = {
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.recalc_rate = tegra30_clk_fixed_recalc_rate,
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.recalc_rate = tegra30_clk_fixed_recalc_rate,
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};
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};
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@@ -17,7 +17,7 @@
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#ifndef __MACH_TEGRA30_CLOCK_H
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#ifndef __MACH_TEGRA30_CLOCK_H
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#define __MACH_TEGRA30_CLOCK_H
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#define __MACH_TEGRA30_CLOCK_H
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extern struct clk_ops tegra_clk_32k_ops;
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extern struct clk_ops tegra30_clk_32k_ops;
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extern struct clk_ops tegra30_clk_m_ops;
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extern struct clk_ops tegra30_clk_m_ops;
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extern struct clk_ops tegra_clk_m_div_ops;
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extern struct clk_ops tegra_clk_m_div_ops;
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extern struct clk_ops tegra_pll_ref_ops;
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extern struct clk_ops tegra_pll_ref_ops;
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@@ -57,7 +57,7 @@ static struct clk_tegra tegra_clk_32k_hw = {
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static struct clk tegra_clk_32k = {
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static struct clk tegra_clk_32k = {
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.name = "clk_32k",
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.name = "clk_32k",
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.hw = &tegra_clk_32k_hw.hw,
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.hw = &tegra_clk_32k_hw.hw,
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.ops = &tegra_clk_32k_ops,
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.ops = &tegra30_clk_32k_ops,
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.flags = CLK_IS_ROOT,
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.flags = CLK_IS_ROOT,
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};
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};
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