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e1000e: fix and commonize code for setting the receive address registers

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Fix e1000e_rar_set() to flush consecutive register writes to avoid write
combining which some parts cannot handle.  Update e1000e_init_rx_addrs()
to call the fixed e1000e_rar_set() instead of duplicating code.

Also change e1000e_rar_set() to _not_ set the Address Valid bit if the MAC
address is all zeros.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Bruce Allan
2010-01-07 16:32:13 +00:00
committed by David S. Miller
parent ca777f9c09
commit b7a9216c5a
1 changed files with 15 additions and 9 deletions
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22
drivers/net/e1000e/lib.c
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@@ -125,6 +125,7 @@ void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
{ {
u32 i; u32 i;
u8 mac_addr[ETH_ALEN] = {0};
/* Setup the receive address */ /* Setup the receive address */
e_dbg("Programming MAC Address into RAR[0]\n"); e_dbg("Programming MAC Address into RAR[0]\n");
@@ -133,12 +134,8 @@ void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
/* Zero out the other (rar_entry_count - 1) receive addresses */ /* Zero out the other (rar_entry_count - 1) receive addresses */
e_dbg("Clearing RAR[1-%u]\n", rar_count-1); e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
for (i = 1; i < rar_count; i++) { for (i = 1; i < rar_count; i++)
E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); e1000e_rar_set(hw, mac_addr, i);
e1e_flush();
E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
e1e_flush();
}
} }
/** /**
@@ -164,10 +161,19 @@ void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
/* If MAC address zero, no need to set the AV bit */
if (rar_low || rar_high)
rar_high |= E1000_RAH_AV; rar_high |= E1000_RAH_AV;
E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); /*
E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); * Some bridges will combine consecutive 32-bit writes into
* a single burst write, which will malfunction on some parts.
* The flushes avoid this.
*/
ew32(RAL(index), rar_low);
e1e_flush();
ew32(RAH(index), rar_high);
e1e_flush();
} }
/** /**