[ARM] 3426/1: ARM: OMAP: 1/8 Update clock framework
Patch from Tony Lindgren Update OMAP clock framework from linux-omap tree. The highlights of the patch are: - Add support for omap730 clocks by Andrzej Zaborowski - Fix compile warnings by Dirk Behme - Add support for using dev id by Tony Lindgren and Komal Shah - Move memory timings and PRCM into separate files by Tony Lindgren Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
committed by
Russell King
Russell King
parent
3267c077e5
commit
b824efae12
@ -28,14 +28,14 @@
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sram.h>
|
||||
#include <asm/arch/prcm.h>
|
||||
|
||||
#include "prcm-regs.h"
|
||||
#include "memory.h"
|
||||
#include "clock.h"
|
||||
|
||||
//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
|
||||
|
||||
static struct prcm_config *curr_prcm_set;
|
||||
static struct memory_timings mem_timings;
|
||||
static u32 curr_perf_level = PRCM_FULL_SPEED;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
@ -54,11 +54,13 @@ static void omap2_sys_clk_recalc(struct clk * clk)
|
||||
|
||||
static u32 omap2_get_dpll_rate(struct clk * tclk)
|
||||
{
|
||||
int dpll_clk, dpll_mult, dpll_div, amult;
|
||||
long long dpll_clk;
|
||||
int dpll_mult, dpll_div, amult;
|
||||
|
||||
dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
|
||||
dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
|
||||
dpll_clk = (tclk->parent->rate * dpll_mult) / (dpll_div + 1);
|
||||
dpll_clk = (long long)tclk->parent->rate * dpll_mult;
|
||||
do_div(dpll_clk, dpll_div + 1);
|
||||
amult = CM_CLKSEL2_PLL & 0x3;
|
||||
dpll_clk *= amult;
|
||||
|
||||
@ -385,75 +387,23 @@ static u32 omap2_dll_force_needed(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
|
||||
{
|
||||
unsigned long dll_cnt;
|
||||
u32 fast_dll = 0;
|
||||
|
||||
mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
|
||||
|
||||
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
|
||||
* In the case of 2422, its ok to use CS1 instead of CS0.
|
||||
*/
|
||||
|
||||
#if 0 /* FIXME: Enable after 24xx cpu detection works */
|
||||
ctype = get_cpu_type();
|
||||
if (cpu_is_omap2422())
|
||||
mem_timings.base_cs = 1;
|
||||
else
|
||||
#endif
|
||||
mem_timings.base_cs = 0;
|
||||
|
||||
if (mem_timings.m_type != M_DDR)
|
||||
return;
|
||||
|
||||
/* With DDR we need to determine the low frequency DLL value */
|
||||
if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
|
||||
mem_timings.dll_mode = M_UNLOCK;
|
||||
else
|
||||
mem_timings.dll_mode = M_LOCK;
|
||||
|
||||
if (mem_timings.base_cs == 0) {
|
||||
fast_dll = SDRC_DLLA_CTRL;
|
||||
dll_cnt = SDRC_DLLA_STATUS & 0xff00;
|
||||
} else {
|
||||
fast_dll = SDRC_DLLB_CTRL;
|
||||
dll_cnt = SDRC_DLLB_STATUS & 0xff00;
|
||||
}
|
||||
if (force_lock_to_unlock_mode) {
|
||||
fast_dll &= ~0xff00;
|
||||
fast_dll |= dll_cnt; /* Current lock mode */
|
||||
}
|
||||
mem_timings.fast_dll_ctrl = fast_dll;
|
||||
|
||||
/* No disruptions, DDR will be offline & C-ABI not followed */
|
||||
omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
|
||||
mem_timings.fast_dll_ctrl,
|
||||
mem_timings.base_cs,
|
||||
force_lock_to_unlock_mode);
|
||||
mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
|
||||
|
||||
/* Turn status into unlock ctrl */
|
||||
mem_timings.slow_dll_ctrl |=
|
||||
((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
|
||||
|
||||
/* 90 degree phase for anything below 133Mhz */
|
||||
mem_timings.slow_dll_ctrl |= (1 << 1);
|
||||
}
|
||||
|
||||
static u32 omap2_reprogram_sdrc(u32 level, u32 force)
|
||||
{
|
||||
u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
|
||||
u32 prev = curr_perf_level, flags;
|
||||
|
||||
if ((curr_perf_level == level) && !force)
|
||||
return prev;
|
||||
|
||||
m_type = omap2_memory_get_type();
|
||||
slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
|
||||
fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
|
||||
|
||||
if (level == PRCM_HALF_SPEED) {
|
||||
local_irq_save(flags);
|
||||
PRCM_VOLTSETUP = 0xffff;
|
||||
omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
|
||||
mem_timings.slow_dll_ctrl,
|
||||
mem_timings.m_type);
|
||||
slow_dll_ctrl, m_type);
|
||||
curr_perf_level = PRCM_HALF_SPEED;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
@ -461,8 +411,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force)
|
||||
local_irq_save(flags);
|
||||
PRCM_VOLTSETUP = 0xffff;
|
||||
omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
|
||||
mem_timings.fast_dll_ctrl,
|
||||
mem_timings.m_type);
|
||||
fast_dll_ctrl, m_type);
|
||||
curr_perf_level = PRCM_FULL_SPEED;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
@ -650,7 +599,7 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
|
||||
case 13: /* dss2 */
|
||||
mask = 0x1; break;
|
||||
case 25: /* usb */
|
||||
mask = 0xf; break;
|
||||
mask = 0x7; break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -33,20 +33,6 @@ static u32 omap2_clksel_get_divisor(struct clk *clk);
|
||||
#define RATE_IN_242X (1 << 0)
|
||||
#define RATE_IN_243X (1 << 1)
|
||||
|
||||
/* Memory timings */
|
||||
#define M_DDR 1
|
||||
#define M_LOCK_CTRL (1 << 2)
|
||||
#define M_UNLOCK 0
|
||||
#define M_LOCK 1
|
||||
|
||||
struct memory_timings {
|
||||
u32 m_type; /* ddr = 1, sdr = 0 */
|
||||
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
|
||||
u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
|
||||
u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
|
||||
u32 base_cs; /* base chip select to use for calculations */
|
||||
};
|
||||
|
||||
/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
|
||||
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
|
||||
* CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
|
||||
@ -731,6 +717,16 @@ static struct clk sys_clkout2 = {
|
||||
.recalc = &omap2_clksel_recalc,
|
||||
};
|
||||
|
||||
static struct clk emul_ck = {
|
||||
.name = "emul_ck",
|
||||
.parent = &func_54m_ck,
|
||||
.flags = CLOCK_IN_OMAP242X,
|
||||
.enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
|
||||
.enable_bit = 0,
|
||||
.recalc = &omap2_propagate_rate,
|
||||
|
||||
};
|
||||
|
||||
/*
|
||||
* MPU clock domain
|
||||
* Clocks:
|
||||
@ -1702,7 +1698,8 @@ static struct clk hdq_fck = {
|
||||
};
|
||||
|
||||
static struct clk i2c2_ick = {
|
||||
.name = "i2c2_ick",
|
||||
.name = "i2c_ick",
|
||||
.id = 2,
|
||||
.parent = &l4_ck,
|
||||
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
|
||||
.enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
|
||||
@ -1711,7 +1708,8 @@ static struct clk i2c2_ick = {
|
||||
};
|
||||
|
||||
static struct clk i2c2_fck = {
|
||||
.name = "i2c2_fck",
|
||||
.name = "i2c_fck",
|
||||
.id = 2,
|
||||
.parent = &func_12m_ck,
|
||||
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
|
||||
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
|
||||
@ -1729,7 +1727,8 @@ static struct clk i2chs2_fck = {
|
||||
};
|
||||
|
||||
static struct clk i2c1_ick = {
|
||||
.name = "i2c1_ick",
|
||||
.name = "i2c_ick",
|
||||
.id = 1,
|
||||
.parent = &l4_ck,
|
||||
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
|
||||
.enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
|
||||
@ -1738,7 +1737,8 @@ static struct clk i2c1_ick = {
|
||||
};
|
||||
|
||||
static struct clk i2c1_fck = {
|
||||
.name = "i2c1_fck",
|
||||
.name = "i2c_fck",
|
||||
.id = 1,
|
||||
.parent = &func_12m_ck,
|
||||
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
|
||||
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
|
||||
@ -1971,6 +1971,7 @@ static struct clk *onchip_clks[] = {
|
||||
&wdt1_osc_ck,
|
||||
&sys_clkout,
|
||||
&sys_clkout2,
|
||||
&emul_ck,
|
||||
/* mpu domain clocks */
|
||||
&mpu_ck,
|
||||
/* dsp domain clocks */
|
||||
|
||||
102
arch/arm/mach-omap2/memory.c
Normal file
102
arch/arm/mach-omap2/memory.c
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-omap2/memory.c
|
||||
*
|
||||
* Memory timing related functions for OMAP24XX
|
||||
*
|
||||
* Copyright (C) 2005 Texas Instruments Inc.
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Tony Lindgren <tony@atomide.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sram.h>
|
||||
|
||||
#include "prcm-regs.h"
|
||||
#include "memory.h"
|
||||
|
||||
static struct memory_timings mem_timings;
|
||||
|
||||
u32 omap2_memory_get_slow_dll_ctrl(void)
|
||||
{
|
||||
return mem_timings.slow_dll_ctrl;
|
||||
}
|
||||
|
||||
u32 omap2_memory_get_fast_dll_ctrl(void)
|
||||
{
|
||||
return mem_timings.fast_dll_ctrl;
|
||||
}
|
||||
|
||||
u32 omap2_memory_get_type(void)
|
||||
{
|
||||
return mem_timings.m_type;
|
||||
}
|
||||
|
||||
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
|
||||
{
|
||||
unsigned long dll_cnt;
|
||||
u32 fast_dll = 0;
|
||||
|
||||
mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
|
||||
|
||||
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
|
||||
* In the case of 2422, its ok to use CS1 instead of CS0.
|
||||
*/
|
||||
if (cpu_is_omap2422())
|
||||
mem_timings.base_cs = 1;
|
||||
else
|
||||
mem_timings.base_cs = 0;
|
||||
|
||||
if (mem_timings.m_type != M_DDR)
|
||||
return;
|
||||
|
||||
/* With DDR we need to determine the low frequency DLL value */
|
||||
if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
|
||||
mem_timings.dll_mode = M_UNLOCK;
|
||||
else
|
||||
mem_timings.dll_mode = M_LOCK;
|
||||
|
||||
if (mem_timings.base_cs == 0) {
|
||||
fast_dll = SDRC_DLLA_CTRL;
|
||||
dll_cnt = SDRC_DLLA_STATUS & 0xff00;
|
||||
} else {
|
||||
fast_dll = SDRC_DLLB_CTRL;
|
||||
dll_cnt = SDRC_DLLB_STATUS & 0xff00;
|
||||
}
|
||||
if (force_lock_to_unlock_mode) {
|
||||
fast_dll &= ~0xff00;
|
||||
fast_dll |= dll_cnt; /* Current lock mode */
|
||||
}
|
||||
/* set fast timings with DLL filter disabled */
|
||||
mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
|
||||
|
||||
/* No disruptions, DDR will be offline & C-ABI not followed */
|
||||
omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
|
||||
mem_timings.fast_dll_ctrl,
|
||||
mem_timings.base_cs,
|
||||
force_lock_to_unlock_mode);
|
||||
mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
|
||||
|
||||
/* Turn status into unlock ctrl */
|
||||
mem_timings.slow_dll_ctrl |=
|
||||
((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
|
||||
|
||||
/* 90 degree phase for anything below 133Mhz + disable DLL filter */
|
||||
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
|
||||
}
|
||||
34
arch/arm/mach-omap2/memory.h
Normal file
34
arch/arm/mach-omap2/memory.h
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-omap2/memory.h
|
||||
*
|
||||
* Interface for memory timing related functions for OMAP24XX
|
||||
*
|
||||
* Copyright (C) 2005 Texas Instruments Inc.
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Tony Lindgren <tony@atomide.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* Memory timings */
|
||||
#define M_DDR 1
|
||||
#define M_LOCK_CTRL (1 << 2)
|
||||
#define M_UNLOCK 0
|
||||
#define M_LOCK 1
|
||||
|
||||
struct memory_timings {
|
||||
u32 m_type; /* ddr = 1, sdr = 0 */
|
||||
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
|
||||
u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
|
||||
u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
|
||||
u32 base_cs; /* base chip select to use for calculations */
|
||||
};
|
||||
|
||||
extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
|
||||
extern u32 omap2_memory_get_slow_dll_ctrl(void);
|
||||
extern u32 omap2_memory_get_fast_dll_ctrl(void);
|
||||
extern u32 omap2_memory_get_type(void);
|
||||
@ -1,5 +1,7 @@
|
||||
/*
|
||||
* prcm.h - Access definations for use in OMAP24XX clock and power management
|
||||
* linux/arch/arm/mach-omap2/prcm-reg.h
|
||||
*
|
||||
* OMAP24XX Power Reset and Clock Management (PRCM) registers
|
||||
*
|
||||
* Copyright (C) 2005 Texas Instruments, Inc.
|
||||
*
|
||||
@ -18,8 +20,8 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
|
||||
#define __ASM_ARM_ARCH_DPM_PRCM_H
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_PRCM_H
|
||||
|
||||
/* SET_PERFORMANCE_LEVEL PARAMETERS */
|
||||
#define PRCM_HALF_SPEED 1
|
||||
@ -159,54 +161,63 @@
|
||||
#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
|
||||
#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
|
||||
#define CM_IDLEST_MDM PRCM_REG32(0xC20)
|
||||
#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
|
||||
#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
|
||||
#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
|
||||
#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
|
||||
#define RM_RSTST_MDM PRCM_REG32(0xC58)
|
||||
#define PM_WKEN_MDM PRCM_REG32(0xCA0)
|
||||
#define PM_WKST_MDM PRCM_REG32(0xCB0)
|
||||
#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
|
||||
#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
|
||||
#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
|
||||
|
||||
/* FIXME: Move to header for 2430 */
|
||||
#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000)
|
||||
#define OMAP24XX_L4_IO_BASE 0x48000000
|
||||
|
||||
#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
|
||||
#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
|
||||
|
||||
#define GPMC_BASE (OMAP24XX_GPMC_BASE)
|
||||
#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset))
|
||||
#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
|
||||
#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))
|
||||
|
||||
#define GPT1_BASE (OMAP24XX_GPT1)
|
||||
/* FIXME: Move these to timer code */
|
||||
#define GPT1_BASE (0x48028000)
|
||||
#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
|
||||
|
||||
/* Misc sysconfig */
|
||||
#define DISPC_SYSCONFIG DISP_REG32(0x410)
|
||||
#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000)
|
||||
#define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000)
|
||||
#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
|
||||
#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10)
|
||||
#define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10)
|
||||
#define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
|
||||
|
||||
//#define DSP_MMU_SYSCONFIG 0x5A000010
|
||||
#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10)
|
||||
//#define IVA_MMU_SYSCONFIG 0x5D000010
|
||||
//#define DSP_DMA_SYSCONFIG 0x00FCC02C
|
||||
#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
|
||||
#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
|
||||
#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10)
|
||||
#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C)
|
||||
#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C)
|
||||
#define GPMC_SYSCONFIG GPMC_REG32(0x010)
|
||||
#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010)
|
||||
#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
|
||||
#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
|
||||
#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
|
||||
//#define IVA_SYSCONFIG 0x5C060010
|
||||
#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10)
|
||||
#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10)
|
||||
#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010)
|
||||
//#define VLYNQ_SYSCONFIG 0x67FFFE10
|
||||
#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
|
||||
#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
|
||||
#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
|
||||
#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
|
||||
#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10)
|
||||
#define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000)
|
||||
#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10)
|
||||
#define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010)
|
||||
|
||||
/* rkw - good cannidates for PM_ to start what nm was trying */
|
||||
#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
|
||||
#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
|
||||
#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
|
||||
#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
|
||||
#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
|
||||
#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
|
||||
#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
|
||||
#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
|
||||
#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
|
||||
#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
|
||||
#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)
|
||||
#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000)
|
||||
#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000)
|
||||
#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000)
|
||||
#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000)
|
||||
#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000)
|
||||
#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000)
|
||||
#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000)
|
||||
#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000)
|
||||
#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000)
|
||||
#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000)
|
||||
#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000)
|
||||
|
||||
/* FIXME: Move these to timer code */
|
||||
#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
|
||||
#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
|
||||
#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
|
||||
@ -220,12 +231,18 @@
|
||||
#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
|
||||
#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
|
||||
|
||||
#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
|
||||
/* FIXME: Move these to gpio code */
|
||||
#define OMAP24XX_GPIO_BASE 0x48018000
|
||||
#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
|
||||
|
||||
#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10))
|
||||
#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10))
|
||||
#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10))
|
||||
#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
|
||||
#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10))
|
||||
#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10))
|
||||
#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10))
|
||||
#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10))
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP243X)
|
||||
#define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10))
|
||||
#endif
|
||||
|
||||
/* GP TIMER 1 */
|
||||
#define GPTIMER1_TISTAT GPT1_REG32(0x014)
|
||||
@ -243,15 +260,15 @@
|
||||
#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
|
||||
|
||||
/* rkw -- base fix up please... */
|
||||
#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018)
|
||||
#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
|
||||
|
||||
/* SDRC */
|
||||
#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060)
|
||||
#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064)
|
||||
#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068)
|
||||
#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C)
|
||||
#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070)
|
||||
#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084)
|
||||
#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
|
||||
#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
|
||||
#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
|
||||
#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
|
||||
#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
|
||||
#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
|
||||
|
||||
/* GPIO 1 */
|
||||
#define GPIO1_BASE GPIOX_BASE(1)
|
||||
@ -278,6 +295,8 @@
|
||||
#define GPIO2_DATAIN GPIO2_REG32(0x038)
|
||||
#define GPIO2_OE GPIO2_REG32(0x034)
|
||||
#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
|
||||
#define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050)
|
||||
#define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054)
|
||||
|
||||
/* GPIO 3 */
|
||||
#define GPIO3_BASE GPIOX_BASE(3)
|
||||
@ -294,6 +313,8 @@
|
||||
#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
|
||||
#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
|
||||
#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
|
||||
#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
|
||||
#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
|
||||
|
||||
/* GPIO 4 */
|
||||
#define GPIO4_BASE GPIOX_BASE(4)
|
||||
@ -311,10 +332,26 @@
|
||||
#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
|
||||
#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP243X)
|
||||
/* GPIO 5 */
|
||||
#define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset)))
|
||||
#define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C)
|
||||
#define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018)
|
||||
#define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C)
|
||||
#define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028)
|
||||
#define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020)
|
||||
#define GPIO5_RISINGDETECT GPIO5_REG32(0x048)
|
||||
#define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C)
|
||||
#define GPIO5_DATAIN GPIO5_REG32(0x038)
|
||||
#define GPIO5_OE GPIO5_REG32(0x034)
|
||||
#define GPIO5_DATAOUT GPIO5_REG32(0x03C)
|
||||
#define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050)
|
||||
#define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054)
|
||||
#endif
|
||||
|
||||
/* IO CONFIG */
|
||||
#define CONTROL_BASE (OMAP24XX_CTRL_BASE)
|
||||
#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset))
|
||||
#define OMAP24XX_CTRL_BASE (L4_24XX_BASE)
|
||||
#define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset))
|
||||
|
||||
#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
|
||||
#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
|
||||
@ -322,15 +359,18 @@
|
||||
#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
|
||||
#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
|
||||
#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
|
||||
#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC)
|
||||
#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */
|
||||
#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
|
||||
#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
|
||||
#define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */
|
||||
#define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */
|
||||
|
||||
/* CONTROL */
|
||||
#define CONTROL_DEVCONF CONTROL_REG32(0x274)
|
||||
#define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8)
|
||||
|
||||
/* INTERRUPT CONTROLLER */
|
||||
#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000)
|
||||
#define INTC_BASE ((L4_24XX_BASE) + 0xfe000)
|
||||
#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
|
||||
|
||||
#define INTC1_U_BASE INTC_REG32(0x000)
|
||||
@ -348,10 +388,12 @@
|
||||
#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
|
||||
#define INTC_SIR_IRQ INTC_REG32(0x040)
|
||||
#define INTC_CONTROL INTC_REG32(0x048)
|
||||
#define INTC_ILR11 INTC_REG32(0x12C)
|
||||
#define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */
|
||||
#define INTC_ILR30 INTC_REG32(0x178)
|
||||
#define INTC_ILR31 INTC_REG32(0x17C)
|
||||
#define INTC_ILR32 INTC_REG32(0x180)
|
||||
#define INTC_ILR37 INTC_REG32(0x194)
|
||||
#define INTC_SYSCONFIG INTC_REG32(0x010)
|
||||
#define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */
|
||||
#define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */
|
||||
|
||||
/* RAM FIREWALL */
|
||||
#define RAMFW_BASE (0x68005000)
|
||||
@ -373,6 +415,24 @@
|
||||
#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
|
||||
#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
|
||||
|
||||
/* GPMC CS1 */
|
||||
#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
|
||||
#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
|
||||
#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
|
||||
#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
|
||||
#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
|
||||
#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
|
||||
#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
|
||||
|
||||
/* GPMC CS3 */
|
||||
#define GPMC_CONFIG1_3 GPMC_REG32(0x0F0)
|
||||
#define GPMC_CONFIG2_3 GPMC_REG32(0x0F4)
|
||||
#define GPMC_CONFIG3_3 GPMC_REG32(0x0F8)
|
||||
#define GPMC_CONFIG4_3 GPMC_REG32(0x0FC)
|
||||
#define GPMC_CONFIG5_3 GPMC_REG32(0x100)
|
||||
#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
|
||||
#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
|
||||
|
||||
/* DSS */
|
||||
#define DSS_CONTROL DISP_REG32(0x040)
|
||||
#define DISPC_CONTROL DISP_REG32(0x440)
|
||||
@ -405,11 +465,15 @@
|
||||
#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
|
||||
#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
|
||||
|
||||
/* Wake up define for board */
|
||||
#define GPIO97 (1 << 1)
|
||||
#define GPIO88 (1 << 24)
|
||||
/* HSUSB Suspend */
|
||||
#define HSUSB_CTRL __REG8(0x480AC001)
|
||||
#define USBOTG_POWER __REG32(0x480AC000)
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
/* HS MMC */
|
||||
#define MMCHS1_SYSCONFIG __REG32(0x4809C010)
|
||||
#define MMCHS2_SYSCONFIG __REG32(0x480b4010)
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif
|
||||
|
||||
40
arch/arm/mach-omap2/prcm.c
Normal file
40
arch/arm/mach-omap2/prcm.c
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-omap2/prcm.c
|
||||
*
|
||||
* OMAP 24xx Power Reset and Clock Management (PRCM) functions
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
*
|
||||
* Written by Tony Lindgren <tony.lindgren@nokia.com>
|
||||
*
|
||||
* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include "prcm-regs.h"
|
||||
|
||||
u32 omap_prcm_get_reset_sources(void)
|
||||
{
|
||||
return RM_RSTST_WKUP & 0x7f;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_prcm_get_reset_sources);
|
||||
|
||||
/* Resets clock rates and reboots the system. Only called from system.h */
|
||||
void omap_prcm_arch_reset(char mode)
|
||||
{
|
||||
u32 rate;
|
||||
struct clk *vclk, *sclk;
|
||||
|
||||
vclk = clk_get(NULL, "virt_prcm_set");
|
||||
sclk = clk_get(NULL, "sys_ck");
|
||||
rate = clk_get_rate(sclk);
|
||||
clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
|
||||
RM_RSTCTRL_WKUP |= 2;
|
||||
}
|
||||
Reference in New Issue
Block a user