[media] rc-core: fix winbond-cir issues
The conversion of winbond-cir to use rc-core seems to have missed a a few bits and pieces which were in my local tree. Kudos to Juan Jesús García de Soria Lucena <skandalfo@gmail.com> for noticing. [mchehab@redhat.com: fix two UTF-8 violations] Signed-off-by: David Härdeman <david@hardeman.nu> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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Mauro Carvalho Chehab
parent
7eb7571546
commit
b87f2eddfa
@@ -6,8 +6,8 @@
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* could probably support others (Winbond WEC102X, NatSemi, etc)
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* could probably support others (Winbond WEC102X, NatSemi, etc)
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* with minor modifications.
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* with minor modifications.
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*
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*
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* Original Author: David H<EFBFBD>rdeman <david@hardeman.nu>
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* Original Author: David Härdeman <david@hardeman.nu>
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* Copyright (C) 2009 - 2010 David H<EFBFBD>rdeman <david@hardeman.nu>
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* Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
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*
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*
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* Dedicated to my daughter Matilda, without whose loving attention this
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* Dedicated to my daughter Matilda, without whose loving attention this
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* driver would have been finished in half the time and with a fraction
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* driver would have been finished in half the time and with a fraction
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@@ -876,18 +876,8 @@ wbcir_init_hw(struct wbcir_data *data)
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/* prescaler 1.0, tx/rx fifo lvl 16 */
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/* prescaler 1.0, tx/rx fifo lvl 16 */
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outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
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outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
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/* Set baud divisor to generate one byte per bit/cell */
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/* Set baud divisor to sample every 10 us */
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switch (protocol) {
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outb(0x0F, data->sbase + WBCIR_REG_SP3_BGDL);
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case IR_PROTOCOL_RC5:
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outb(0xA7, data->sbase + WBCIR_REG_SP3_BGDL);
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break;
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case IR_PROTOCOL_RC6:
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outb(0x53, data->sbase + WBCIR_REG_SP3_BGDL);
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break;
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case IR_PROTOCOL_NEC:
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outb(0x69, data->sbase + WBCIR_REG_SP3_BGDL);
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break;
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}
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outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
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outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
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/* Set CEIR mode */
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/* Set CEIR mode */
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@@ -896,9 +886,9 @@ wbcir_init_hw(struct wbcir_data *data)
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inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
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inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
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inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
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inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
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/* Disable RX demod, run-length encoding/decoding, set freq span */
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/* Disable RX demod, enable run-length enc/dec, set freq span */
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wbcir_select_bank(data, WBCIR_BANK_7);
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wbcir_select_bank(data, WBCIR_BANK_7);
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outb(0x10, data->sbase + WBCIR_REG_SP3_RCCFG);
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outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
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/* Disable timer */
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/* Disable timer */
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wbcir_select_bank(data, WBCIR_BANK_4);
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wbcir_select_bank(data, WBCIR_BANK_4);
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