netdev/phy/icplus: Correct broken phy_init code
The code for ip1001_config_init() was totally broken if you were not using RGMII. Instead of returning an error code or zero it actually returned the value in the IP1001_SPEC_CTRL_STATUS_2 register. It was also trying to set the IP1001_APS_ON bit , but never actually wrote back the register. The error checking was also incorrect in both this function and the reset function, so this patch fixes that up in a consistent fashion. Signed-off-by: David McKay <david.mckay@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller
parent
03606895cd
commit
b8e3995af4
@@ -98,20 +98,24 @@ static int ip175c_config_init(struct phy_device *phydev)
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static int ip1xx_reset(struct phy_device *phydev)
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static int ip1xx_reset(struct phy_device *phydev)
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{
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{
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int err, bmcr;
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int bmcr;
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/* Software Reset PHY */
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/* Software Reset PHY */
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bmcr = phy_read(phydev, MII_BMCR);
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bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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bmcr |= BMCR_RESET;
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bmcr |= BMCR_RESET;
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err = phy_write(phydev, MII_BMCR, bmcr);
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bmcr = phy_write(phydev, MII_BMCR, bmcr);
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if (err < 0)
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if (bmcr < 0)
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return err;
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return bmcr;
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do {
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do {
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bmcr = phy_read(phydev, MII_BMCR);
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bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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} while (bmcr & BMCR_RESET);
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} while (bmcr & BMCR_RESET);
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return err;
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return 0;
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}
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}
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static int ip1001_config_init(struct phy_device *phydev)
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static int ip1001_config_init(struct phy_device *phydev)
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@@ -124,7 +128,10 @@ static int ip1001_config_init(struct phy_device *phydev)
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/* Enable Auto Power Saving mode */
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/* Enable Auto Power Saving mode */
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c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
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c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
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if (c < 0)
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return c;
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c |= IP1001_APS_ON;
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c |= IP1001_APS_ON;
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c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
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if (c < 0)
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if (c < 0)
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return c;
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return c;
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@@ -132,11 +139,16 @@ static int ip1001_config_init(struct phy_device *phydev)
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/* Additional delay (2ns) used to adjust RX clock phase
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/* Additional delay (2ns) used to adjust RX clock phase
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* at RGMII interface */
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* at RGMII interface */
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c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
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c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
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if (c < 0)
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return c;
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c |= IP1001_PHASE_SEL_MASK;
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c |= IP1001_PHASE_SEL_MASK;
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c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
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c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
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if (c < 0)
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return c;
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}
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}
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return c;
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return 0;
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}
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}
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static int ip101a_config_init(struct phy_device *phydev)
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static int ip101a_config_init(struct phy_device *phydev)
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