x86: TSC deadline definitions
This pre-defination is preparing for KVM tsc deadline timer emulation, but theirself are not kvm specific. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
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@@ -229,6 +229,8 @@
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_TSCDEADLINE 0x000006e0
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_REV 0x0000008b
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