[POWERPC] Use the genirq framework
This adapts the generic powerpc interrupt handling code, and all of the platforms except for the embedded 6xx machines, to use the new genirq framework. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
committed by
Paul Mackerras
Paul Mackerras
parent
5a43a066b1
commit
b9e5b4e6a9
@@ -37,64 +37,51 @@
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struct iic {
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struct cbe_iic_thread_regs __iomem *regs;
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u8 target_id;
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u8 eoi_stack[16];
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int eoi_ptr;
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};
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static DEFINE_PER_CPU(struct iic, iic);
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void iic_local_enable(void)
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static void iic_mask(unsigned int irq)
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{
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}
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static void iic_unmask(unsigned int irq)
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{
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}
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static void iic_eoi(unsigned int irq)
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{
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struct iic *iic = &__get_cpu_var(iic);
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u64 tmp;
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/*
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* There seems to be a bug that is present in DD2.x CPUs
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* and still only partially fixed in DD3.1.
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* This bug causes a value written to the priority register
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* not to make it there, resulting in a system hang unless we
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* write it again.
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* Masking with 0xf0 is done because the Cell BE does not
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* implement the lower four bits of the interrupt priority,
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* they always read back as zeroes, although future CPUs
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* might implement different bits.
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*/
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do {
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out_be64(&iic->regs->prio, 0xff);
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tmp = in_be64(&iic->regs->prio);
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} while ((tmp & 0xf0) != 0xf0);
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out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
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BUG_ON(iic->eoi_ptr < 0);
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}
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void iic_local_disable(void)
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{
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out_be64(&__get_cpu_var(iic).regs->prio, 0x0);
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}
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static unsigned int iic_startup(unsigned int irq)
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{
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return 0;
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}
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static void iic_enable(unsigned int irq)
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{
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iic_local_enable();
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}
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static void iic_disable(unsigned int irq)
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{
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}
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static void iic_end(unsigned int irq)
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{
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iic_local_enable();
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}
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static struct hw_interrupt_type iic_pic = {
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static struct irq_chip iic_chip = {
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.typename = " CELL-IIC ",
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.startup = iic_startup,
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.enable = iic_enable,
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.disable = iic_disable,
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.end = iic_end,
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.mask = iic_mask,
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.unmask = iic_unmask,
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.eoi = iic_eoi,
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};
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/* XXX All of this has to be reworked completely. We need to assign a real
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* interrupt numbers to the external interrupts and remove all the hard coded
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* interrupt maps (rely on the device-tree whenever possible).
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*
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* Basically, my scheme is to define the "pendings" bits to be the HW interrupt
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* number (ignoring the data and flags here). That means we can sort-of split
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* external sources based on priority, and we can use request_irq() on pretty
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* much anything.
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*
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* For spider or axon, they have their own interrupt space. spider will just have
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* local "hardward" interrupts 0...xx * node stride. The node stride is not
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* necessary (separate interrupt chips will have separate HW number space), but
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* will allow to be compatible with existing device-trees.
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*
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* All of thise little world will get a standard remapping scheme to map those HW
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* numbers into the linux flat irq number space.
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*/
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static int iic_external_get_irq(struct cbe_iic_pending_bits pending)
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{
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int irq;
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@@ -118,9 +105,10 @@ static int iic_external_get_irq(struct cbe_iic_pending_bits pending)
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*/
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if (pending.class != 2)
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break;
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irq = IIC_EXT_OFFSET
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+ spider_get_irq(node)
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+ node * IIC_NODE_STRIDE;
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/* TODO: We might want to silently ignore cascade interrupts
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* when no cascade handler exist yet
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*/
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irq = IIC_EXT_CASCADE + node * IIC_NODE_STRIDE;
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break;
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case 0x01 ... 0x04:
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case 0x07 ... 0x0a:
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@@ -152,6 +140,8 @@ int iic_get_irq(struct pt_regs *regs)
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iic = &__get_cpu_var(iic);
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*(unsigned long *) &pending =
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in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
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iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
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BUG_ON(iic->eoi_ptr > 15);
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irq = -1;
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if (pending.flags & CBE_IIC_IRQ_VALID) {
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@@ -172,7 +162,7 @@ int iic_get_irq(struct pt_regs *regs)
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/* hardcoded part to be compatible with older firmware */
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static int setup_iic_hardcoded(void)
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static int __init setup_iic_hardcoded(void)
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{
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struct device_node *np;
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int nodeid, cpu;
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@@ -207,12 +197,13 @@ static int setup_iic_hardcoded(void)
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printk(KERN_INFO "IIC for CPU %d at %lx\n", cpu, regs);
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iic->regs = ioremap(regs, sizeof(struct cbe_iic_thread_regs));
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iic->target_id = (nodeid << 4) + ((cpu & 1) ? 0xf : 0xe);
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iic->eoi_stack[0] = 0xff;
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}
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return 0;
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}
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static int setup_iic(void)
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static int __init setup_iic(void)
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{
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struct device_node *dn;
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unsigned long *regs;
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@@ -248,11 +239,14 @@ static int setup_iic(void)
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iic = &per_cpu(iic, np[0]);
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iic->regs = ioremap(regs[0], sizeof(struct cbe_iic_thread_regs));
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iic->target_id = ((np[0] & 2) << 3) + ((np[0] & 1) ? 0xf : 0xe);
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iic->eoi_stack[0] = 0xff;
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printk("IIC for CPU %d at %lx mapped to %p\n", np[0], regs[0], iic->regs);
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iic = &per_cpu(iic, np[1]);
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iic->regs = ioremap(regs[2], sizeof(struct cbe_iic_thread_regs));
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iic->target_id = ((np[1] & 2) << 3) + ((np[1] & 1) ? 0xf : 0xe);
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iic->eoi_stack[0] = 0xff;
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printk("IIC for CPU %d at %lx mapped to %p\n", np[1], regs[2], iic->regs);
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found++;
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@@ -304,10 +298,10 @@ static void iic_request_ipi(int ipi, const char *name)
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int irq;
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irq = iic_ipi_to_irq(ipi);
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/* IPIs are marked IRQF_DISABLED as they must run with irqs
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* disabled */
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get_irq_desc(irq)->chip = &iic_pic;
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get_irq_desc(irq)->status |= IRQ_PER_CPU;
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set_irq_chip_and_handler(irq, &iic_chip, handle_percpu_irq);
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request_irq(irq, iic_ipi_action, IRQF_DISABLED, name, NULL);
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}
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@@ -321,20 +315,26 @@ void iic_request_IPIs(void)
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}
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#endif /* CONFIG_SMP */
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static void iic_setup_spe_handlers(void)
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static void __init iic_setup_builtin_handlers(void)
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{
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int be, isrc;
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/* Assume two threads per BE are present */
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/* XXX FIXME: Assume two threads per BE are present */
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for (be=0; be < num_present_cpus() / 2; be++) {
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int irq;
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/* setup SPE chip and handlers */
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for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
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int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
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get_irq_desc(irq)->chip = &iic_pic;
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irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
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set_irq_chip_and_handler(irq, &iic_chip, handle_fasteoi_irq);
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}
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/* setup cascade chip */
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irq = IIC_EXT_CASCADE + be * IIC_NODE_STRIDE;
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set_irq_chip_and_handler(irq, &iic_chip, handle_fasteoi_irq);
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}
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}
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void iic_init_IRQ(void)
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void __init iic_init_IRQ(void)
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{
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int cpu, irq_offset;
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struct iic *iic;
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@@ -348,5 +348,6 @@ void iic_init_IRQ(void)
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if (iic->regs)
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out_be64(&iic->regs->prio, 0xff);
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}
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iic_setup_spe_handlers();
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iic_setup_builtin_handlers();
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}
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