[POWERPC] Use the genirq framework
This adapts the generic powerpc interrupt handling code, and all of the platforms except for the embedded 6xx machines, to use the new genirq framework. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
committed by
Paul Mackerras
Paul Mackerras
parent
5a43a066b1
commit
b9e5b4e6a9
@ -31,23 +31,6 @@
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#include "xics.h"
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static unsigned int xics_startup(unsigned int irq);
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static void xics_enable_irq(unsigned int irq);
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static void xics_disable_irq(unsigned int irq);
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static void xics_mask_and_ack_irq(unsigned int irq);
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static void xics_end_irq(unsigned int irq);
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static void xics_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
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static struct hw_interrupt_type xics_pic = {
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.typename = " XICS ",
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.startup = xics_startup,
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.enable = xics_enable_irq,
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.disable = xics_disable_irq,
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.ack = xics_mask_and_ack_irq,
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.end = xics_end_irq,
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.set_affinity = xics_set_affinity
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};
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/* This is used to map real irq numbers to virtual */
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static struct radix_tree_root irq_map = RADIX_TREE_INIT(GFP_ATOMIC);
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@ -98,48 +81,34 @@ static int ibm_set_xive;
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static int ibm_int_on;
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static int ibm_int_off;
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typedef struct {
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int (*xirr_info_get)(int cpu);
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void (*xirr_info_set)(int cpu, int val);
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void (*cppr_info)(int cpu, u8 val);
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void (*qirr_info)(int cpu, u8 val);
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} xics_ops;
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/* Direct HW low level accessors */
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/* SMP */
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static int pSeries_xirr_info_get(int n_cpu)
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static inline int direct_xirr_info_get(int n_cpu)
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{
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return in_be32(&xics_per_cpu[n_cpu]->xirr.word);
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}
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static void pSeries_xirr_info_set(int n_cpu, int value)
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static inline void direct_xirr_info_set(int n_cpu, int value)
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{
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out_be32(&xics_per_cpu[n_cpu]->xirr.word, value);
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}
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static void pSeries_cppr_info(int n_cpu, u8 value)
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static inline void direct_cppr_info(int n_cpu, u8 value)
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{
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out_8(&xics_per_cpu[n_cpu]->xirr.bytes[0], value);
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}
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static void pSeries_qirr_info(int n_cpu, u8 value)
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static inline void direct_qirr_info(int n_cpu, u8 value)
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{
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out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
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}
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static xics_ops pSeries_ops = {
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pSeries_xirr_info_get,
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pSeries_xirr_info_set,
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pSeries_cppr_info,
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pSeries_qirr_info
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};
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static xics_ops *ops = &pSeries_ops;
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/* LPAR low level accessors */
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/* LPAR */
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static inline long plpar_eoi(unsigned long xirr)
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{
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return plpar_hcall_norets(H_EOI, xirr);
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@ -161,7 +130,7 @@ static inline long plpar_xirr(unsigned long *xirr_ret)
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return plpar_hcall(H_XIRR, 0, 0, 0, 0, xirr_ret, &dummy, &dummy);
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}
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static int pSeriesLP_xirr_info_get(int n_cpu)
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static inline int lpar_xirr_info_get(int n_cpu)
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{
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unsigned long lpar_rc;
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unsigned long return_value;
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@ -172,7 +141,7 @@ static int pSeriesLP_xirr_info_get(int n_cpu)
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return (int)return_value;
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}
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static void pSeriesLP_xirr_info_set(int n_cpu, int value)
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static inline void lpar_xirr_info_set(int n_cpu, int value)
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{
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unsigned long lpar_rc;
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unsigned long val64 = value & 0xffffffff;
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@ -183,7 +152,7 @@ static void pSeriesLP_xirr_info_set(int n_cpu, int value)
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val64);
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}
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void pSeriesLP_cppr_info(int n_cpu, u8 value)
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static inline void lpar_cppr_info(int n_cpu, u8 value)
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{
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unsigned long lpar_rc;
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@ -192,7 +161,7 @@ void pSeriesLP_cppr_info(int n_cpu, u8 value)
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panic("bad return code cppr - rc = %lx\n", lpar_rc);
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}
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static void pSeriesLP_qirr_info(int n_cpu , u8 value)
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static inline void lpar_qirr_info(int n_cpu , u8 value)
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{
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unsigned long lpar_rc;
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@ -201,36 +170,9 @@ static void pSeriesLP_qirr_info(int n_cpu , u8 value)
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panic("bad return code qirr - rc = %lx\n", lpar_rc);
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}
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xics_ops pSeriesLP_ops = {
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pSeriesLP_xirr_info_get,
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pSeriesLP_xirr_info_set,
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pSeriesLP_cppr_info,
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pSeriesLP_qirr_info
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};
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static unsigned int xics_startup(unsigned int virq)
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{
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unsigned int irq;
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/* High level handlers and init code */
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irq = irq_offset_down(virq);
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if (radix_tree_insert(&irq_map, virt_irq_to_real(irq),
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&virt_irq_to_real_map[irq]) == -ENOMEM)
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printk(KERN_CRIT "Out of memory creating real -> virtual"
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" IRQ mapping for irq %u (real 0x%x)\n",
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virq, virt_irq_to_real(irq));
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xics_enable_irq(virq);
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return 0; /* return value is ignored */
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}
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static unsigned int real_irq_to_virt(unsigned int real_irq)
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{
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unsigned int *ptr;
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ptr = radix_tree_lookup(&irq_map, real_irq);
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if (ptr == NULL)
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return NO_IRQ;
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return ptr - virt_irq_to_real_map;
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}
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#ifdef CONFIG_SMP
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static int get_irq_server(unsigned int irq)
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@ -264,17 +206,20 @@ static int get_irq_server(unsigned int irq)
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}
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#endif
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static void xics_enable_irq(unsigned int virq)
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static void xics_unmask_irq(unsigned int virq)
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{
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unsigned int irq;
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int call_status;
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unsigned int server;
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irq = virt_irq_to_real(irq_offset_down(virq));
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if (irq == XICS_IPI)
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WARN_ON(irq == NO_IRQ);
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if (irq == XICS_IPI || irq == NO_IRQ)
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return;
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server = get_irq_server(virq);
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
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DEFAULT_PRIORITY);
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if (call_status != 0) {
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@ -293,7 +238,7 @@ static void xics_enable_irq(unsigned int virq)
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}
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}
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static void xics_disable_real_irq(unsigned int irq)
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static void xics_mask_real_irq(unsigned int irq)
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{
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int call_status;
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unsigned int server;
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@ -318,75 +263,104 @@ static void xics_disable_real_irq(unsigned int irq)
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}
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}
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static void xics_disable_irq(unsigned int virq)
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static void xics_mask_irq(unsigned int virq)
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{
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unsigned int irq;
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irq = virt_irq_to_real(irq_offset_down(virq));
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xics_disable_real_irq(irq);
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WARN_ON(irq == NO_IRQ);
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if (irq != NO_IRQ)
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xics_mask_real_irq(irq);
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}
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static void xics_end_irq(unsigned int irq)
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static void xics_set_irq_revmap(unsigned int virq)
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{
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unsigned int irq;
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irq = irq_offset_down(virq);
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if (radix_tree_insert(&irq_map, virt_irq_to_real(irq),
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&virt_irq_to_real_map[irq]) == -ENOMEM)
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printk(KERN_CRIT "Out of memory creating real -> virtual"
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" IRQ mapping for irq %u (real 0x%x)\n",
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virq, virt_irq_to_real(irq));
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}
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static unsigned int xics_startup(unsigned int virq)
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{
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xics_set_irq_revmap(virq);
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xics_unmask_irq(virq);
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return 0;
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}
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static unsigned int real_irq_to_virt(unsigned int real_irq)
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{
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unsigned int *ptr;
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ptr = radix_tree_lookup(&irq_map, real_irq);
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if (ptr == NULL)
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return NO_IRQ;
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return ptr - virt_irq_to_real_map;
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}
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static void xics_eoi_direct(unsigned int irq)
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{
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int cpu = smp_processor_id();
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iosync();
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ops->xirr_info_set(cpu, ((0xff << 24) |
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direct_xirr_info_set(cpu, ((0xff << 24) |
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(virt_irq_to_real(irq_offset_down(irq)))));
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}
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static void xics_eoi_lpar(unsigned int irq)
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{
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int cpu = smp_processor_id();
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iosync();
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lpar_xirr_info_set(cpu, ((0xff << 24) |
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(virt_irq_to_real(irq_offset_down(irq)))));
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}
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static void xics_mask_and_ack_irq(unsigned int irq)
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static inline int xics_remap_irq(int vec)
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{
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int cpu = smp_processor_id();
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if (irq < irq_offset_value()) {
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i8259_pic.ack(irq);
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iosync();
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ops->xirr_info_set(cpu, ((0xff<<24) |
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xics_irq_8259_cascade_real));
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iosync();
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}
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}
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int xics_get_irq(struct pt_regs *regs)
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{
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unsigned int cpu = smp_processor_id();
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unsigned int vec;
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int irq;
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vec = ops->xirr_info_get(cpu);
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/* (vec >> 24) == old priority */
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vec &= 0x00ffffff;
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/* for sanity, this had better be < NR_IRQS - 16 */
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if (vec == xics_irq_8259_cascade_real) {
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irq = i8259_irq(regs);
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xics_end_irq(irq_offset_up(xics_irq_8259_cascade));
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} else if (vec == XICS_IRQ_SPURIOUS) {
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irq = -1;
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} else {
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irq = real_irq_to_virt(vec);
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if (irq == NO_IRQ)
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irq = real_irq_to_virt_slowpath(vec);
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if (irq == NO_IRQ) {
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printk(KERN_ERR "Interrupt %u (real) is invalid,"
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" disabling it.\n", vec);
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xics_disable_real_irq(vec);
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} else
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irq = irq_offset_up(irq);
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}
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return irq;
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if (vec == XICS_IRQ_SPURIOUS)
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return NO_IRQ;
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irq = real_irq_to_virt(vec);
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if (irq == NO_IRQ)
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irq = real_irq_to_virt_slowpath(vec);
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if (likely(irq != NO_IRQ))
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return irq_offset_up(irq);
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printk(KERN_ERR "Interrupt %u (real) is invalid,"
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" disabling it.\n", vec);
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xics_mask_real_irq(vec);
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return NO_IRQ;
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}
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static int xics_get_irq_direct(struct pt_regs *regs)
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{
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unsigned int cpu = smp_processor_id();
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return xics_remap_irq(direct_xirr_info_get(cpu));
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}
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static int xics_get_irq_lpar(struct pt_regs *regs)
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{
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unsigned int cpu = smp_processor_id();
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return xics_remap_irq(lpar_xirr_info_get(cpu));
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}
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#ifdef CONFIG_SMP
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static irqreturn_t xics_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t xics_ipi_dispatch(int cpu, struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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ops->qirr_info(cpu, 0xff);
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WARN_ON(cpu_is_offline(cpu));
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while (xics_ipi_message[cpu].value) {
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@ -418,18 +392,108 @@ static irqreturn_t xics_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
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return IRQ_HANDLED;
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}
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static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id, struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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direct_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu, regs);
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}
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static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id, struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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lpar_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu, regs);
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}
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void xics_cause_IPI(int cpu)
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{
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ops->qirr_info(cpu, IPI_PRIORITY);
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if (firmware_has_feature(FW_FEATURE_LPAR))
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lpar_qirr_info(cpu, IPI_PRIORITY);
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else
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direct_qirr_info(cpu, IPI_PRIORITY);
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}
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#endif /* CONFIG_SMP */
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static void xics_set_cpu_priority(int cpu, unsigned char cppr)
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{
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if (firmware_has_feature(FW_FEATURE_LPAR))
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lpar_cppr_info(cpu, cppr);
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else
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direct_cppr_info(cpu, cppr);
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iosync();
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}
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static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
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{
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unsigned int irq;
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int status;
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int xics_status[2];
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unsigned long newmask;
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cpumask_t tmp = CPU_MASK_NONE;
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irq = virt_irq_to_real(irq_offset_down(virq));
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if (irq == XICS_IPI || irq == NO_IRQ)
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return;
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status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
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if (status) {
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printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
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"returns %d\n", irq, status);
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return;
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}
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/* For the moment only implement delivery to all cpus or one cpu */
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if (cpus_equal(cpumask, CPU_MASK_ALL)) {
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newmask = default_distrib_server;
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} else {
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cpus_and(tmp, cpu_online_map, cpumask);
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if (cpus_empty(tmp))
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return;
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newmask = get_hard_smp_processor_id(first_cpu(tmp));
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}
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status = rtas_call(ibm_set_xive, 3, 1, NULL,
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irq, newmask, xics_status[1]);
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if (status) {
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printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
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"returns %d\n", irq, status);
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return;
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}
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}
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static struct irq_chip xics_pic_direct = {
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.typename = " XICS ",
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.startup = xics_startup,
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.mask = xics_mask_irq,
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.unmask = xics_unmask_irq,
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.eoi = xics_eoi_direct,
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.set_affinity = xics_set_affinity
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};
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static struct irq_chip xics_pic_lpar = {
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.typename = " XICS ",
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.startup = xics_startup,
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.mask = xics_mask_irq,
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.unmask = xics_unmask_irq,
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.eoi = xics_eoi_lpar,
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.set_affinity = xics_set_affinity
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};
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void xics_setup_cpu(void)
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{
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int cpu = smp_processor_id();
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ops->cppr_info(cpu, 0xff);
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iosync();
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xics_set_cpu_priority(cpu, 0xff);
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/*
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* Put the calling processor into the GIQ. This is really only
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@ -453,6 +517,7 @@ void xics_init_IRQ(void)
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unsigned long addr;
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unsigned long size;
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} intnodes[NR_CPUS];
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struct irq_chip *chip;
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ppc64_boot_msg(0x20, "XICS Init");
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@ -519,26 +584,10 @@ nextnode:
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intr_base = intnodes[0].addr;
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intr_size = intnodes[0].size;
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np = of_find_node_by_type(NULL, "interrupt-controller");
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if (!np) {
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printk(KERN_DEBUG "xics: no ISA interrupt controller\n");
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xics_irq_8259_cascade_real = -1;
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xics_irq_8259_cascade = -1;
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} else {
|
||||
ireg = (uint *) get_property(np, "interrupts", NULL);
|
||||
if (!ireg)
|
||||
panic("xics_init_IRQ: can't find ISA interrupts property");
|
||||
|
||||
xics_irq_8259_cascade_real = *ireg;
|
||||
xics_irq_8259_cascade
|
||||
= virt_irq_create_mapping(xics_irq_8259_cascade_real);
|
||||
i8259_init(0, 0);
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
if (firmware_has_feature(FW_FEATURE_LPAR))
|
||||
ops = &pSeriesLP_ops;
|
||||
else {
|
||||
if (firmware_has_feature(FW_FEATURE_LPAR)) {
|
||||
ppc_md.get_irq = xics_get_irq_lpar;
|
||||
chip = &xics_pic_lpar;
|
||||
} else {
|
||||
#ifdef CONFIG_SMP
|
||||
for_each_possible_cpu(i) {
|
||||
int hard_id;
|
||||
@ -554,32 +603,54 @@ nextnode:
|
||||
#else
|
||||
xics_per_cpu[0] = ioremap(intr_base, intr_size);
|
||||
#endif /* CONFIG_SMP */
|
||||
ppc_md.get_irq = xics_get_irq_direct;
|
||||
chip = &xics_pic_direct;
|
||||
|
||||
}
|
||||
|
||||
for (i = irq_offset_value(); i < NR_IRQS; ++i)
|
||||
get_irq_desc(i)->chip = &xics_pic;
|
||||
for (i = irq_offset_value(); i < NR_IRQS; ++i) {
|
||||
/* All IRQs on XICS are level for now. MSI code may want to modify
|
||||
* that for reporting purposes
|
||||
*/
|
||||
get_irq_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, chip, handle_fasteoi_irq);
|
||||
}
|
||||
|
||||
xics_setup_cpu();
|
||||
|
||||
ppc64_boot_msg(0x21, "XICS Done");
|
||||
}
|
||||
|
||||
/*
|
||||
* We cant do this in init_IRQ because we need the memory subsystem up for
|
||||
* request_irq()
|
||||
*/
|
||||
static int __init xics_setup_i8259(void)
|
||||
static int xics_setup_8259_cascade(void)
|
||||
{
|
||||
if (ppc64_interrupt_controller == IC_PPC_XIC &&
|
||||
xics_irq_8259_cascade != -1) {
|
||||
if (request_irq(irq_offset_up(xics_irq_8259_cascade),
|
||||
no_action, 0, "8259 cascade", NULL))
|
||||
printk(KERN_ERR "xics_setup_i8259: couldn't get 8259 "
|
||||
"cascade\n");
|
||||
struct device_node *np;
|
||||
uint *ireg;
|
||||
|
||||
np = of_find_node_by_type(NULL, "interrupt-controller");
|
||||
if (np == NULL) {
|
||||
printk(KERN_WARNING "xics: no ISA interrupt controller\n");
|
||||
xics_irq_8259_cascade_real = -1;
|
||||
xics_irq_8259_cascade = -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ireg = (uint *) get_property(np, "interrupts", NULL);
|
||||
if (!ireg)
|
||||
panic("xics_init_IRQ: can't find ISA interrupts property");
|
||||
|
||||
xics_irq_8259_cascade_real = *ireg;
|
||||
xics_irq_8259_cascade = irq_offset_up
|
||||
(virt_irq_create_mapping(xics_irq_8259_cascade_real));
|
||||
i8259_init(0, 0);
|
||||
of_node_put(np);
|
||||
|
||||
xics_set_irq_revmap(xics_irq_8259_cascade);
|
||||
set_irq_chained_handler(xics_irq_8259_cascade, pSeries_8259_cascade);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(xics_setup_i8259);
|
||||
arch_initcall(xics_setup_8259_cascade);
|
||||
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void xics_request_IPIs(void)
|
||||
@ -590,61 +661,22 @@ void xics_request_IPIs(void)
|
||||
* IPIs are marked IRQF_DISABLED as they must run with irqs
|
||||
* disabled
|
||||
*/
|
||||
request_irq(irq_offset_up(XICS_IPI), xics_ipi_action,
|
||||
IRQF_DISABLED, "IPI", NULL);
|
||||
get_irq_desc(irq_offset_up(XICS_IPI))->status |= IRQ_PER_CPU;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
|
||||
{
|
||||
unsigned int irq;
|
||||
int status;
|
||||
int xics_status[2];
|
||||
unsigned long newmask;
|
||||
cpumask_t tmp = CPU_MASK_NONE;
|
||||
|
||||
irq = virt_irq_to_real(irq_offset_down(virq));
|
||||
if (irq == XICS_IPI || irq == NO_IRQ)
|
||||
return;
|
||||
|
||||
status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
|
||||
|
||||
if (status) {
|
||||
printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
|
||||
"returns %d\n", irq, status);
|
||||
return;
|
||||
}
|
||||
|
||||
/* For the moment only implement delivery to all cpus or one cpu */
|
||||
if (cpus_equal(cpumask, CPU_MASK_ALL)) {
|
||||
newmask = default_distrib_server;
|
||||
} else {
|
||||
cpus_and(tmp, cpu_online_map, cpumask);
|
||||
if (cpus_empty(tmp))
|
||||
return;
|
||||
newmask = get_hard_smp_processor_id(first_cpu(tmp));
|
||||
}
|
||||
|
||||
status = rtas_call(ibm_set_xive, 3, 1, NULL,
|
||||
irq, newmask, xics_status[1]);
|
||||
|
||||
if (status) {
|
||||
printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
|
||||
"returns %d\n", irq, status);
|
||||
return;
|
||||
}
|
||||
set_irq_handler(irq_offset_up(XICS_IPI), handle_percpu_irq);
|
||||
if (firmware_has_feature(FW_FEATURE_LPAR))
|
||||
request_irq(irq_offset_up(XICS_IPI), xics_ipi_action_lpar,
|
||||
SA_INTERRUPT, "IPI", NULL);
|
||||
else
|
||||
request_irq(irq_offset_up(XICS_IPI), xics_ipi_action_direct,
|
||||
SA_INTERRUPT, "IPI", NULL);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
void xics_teardown_cpu(int secondary)
|
||||
{
|
||||
struct irq_desc *desc = get_irq_desc(irq_offset_up(XICS_IPI));
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
ops->cppr_info(cpu, 0x00);
|
||||
iosync();
|
||||
|
||||
/* Clear IPI */
|
||||
ops->qirr_info(cpu, 0xff);
|
||||
xics_set_cpu_priority(cpu, 0);
|
||||
|
||||
/*
|
||||
* we need to EOI the IPI if we got here from kexec down IPI
|
||||
@ -653,7 +685,8 @@ void xics_teardown_cpu(int secondary)
|
||||
* should we be flagging idle loop instead?
|
||||
* or creating some task to be scheduled?
|
||||
*/
|
||||
ops->xirr_info_set(cpu, XICS_IPI);
|
||||
if (desc->chip && desc->chip->eoi)
|
||||
desc->chip->eoi(XICS_IPI);
|
||||
|
||||
/*
|
||||
* Some machines need to have at least one cpu in the GIQ,
|
||||
@ -674,8 +707,7 @@ void xics_migrate_irqs_away(void)
|
||||
unsigned int irq, virq, cpu = smp_processor_id();
|
||||
|
||||
/* Reject any interrupt that was queued to us... */
|
||||
ops->cppr_info(cpu, 0);
|
||||
iosync();
|
||||
xics_set_cpu_priority(cpu, 0);
|
||||
|
||||
/* remove ourselves from the global interrupt queue */
|
||||
status = rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
|
||||
@ -683,11 +715,10 @@ void xics_migrate_irqs_away(void)
|
||||
WARN_ON(status < 0);
|
||||
|
||||
/* Allow IPIs again... */
|
||||
ops->cppr_info(cpu, DEFAULT_PRIORITY);
|
||||
iosync();
|
||||
xics_set_cpu_priority(cpu, DEFAULT_PRIORITY);
|
||||
|
||||
for_each_irq(virq) {
|
||||
irq_desc_t *desc;
|
||||
struct irq_desc *desc;
|
||||
int xics_status[2];
|
||||
unsigned long flags;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user