x86, um: ... and asm-x86 move
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Al Viro
H. Peter Anvin
199
arch/x86/include/asm/apic.h
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199
arch/x86/include/asm/apic.h
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#ifndef ASM_X86__APIC_H
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#define ASM_X86__APIC_H
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#include <linux/pm.h>
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#include <linux/delay.h>
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#include <asm/alternative.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/cpufeature.h>
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#include <asm/msr.h>
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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extern void generic_apic_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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extern unsigned int apic_verbosity;
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extern int local_apic_timer_c2_ok;
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extern int disable_apic;
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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#endif
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extern int is_vsmp_box(void);
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extern void xapic_wait_icr_idle(void);
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extern u32 safe_xapic_wait_icr_idle(void);
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extern u64 xapic_icr_read(void);
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extern void xapic_icr_write(u32, u32);
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extern int setup_profiling_timer(unsigned int);
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static inline void native_apic_mem_write(u32 reg, u32 v)
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{
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volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
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alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
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ASM_OUTPUT2("=r" (v), "=m" (*addr)),
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ASM_OUTPUT2("0" (v), "m" (*addr)));
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}
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static inline u32 native_apic_mem_read(u32 reg)
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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static inline void native_apic_msr_write(u32 reg, u32 v)
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{
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if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
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reg == APIC_LVR)
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return;
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wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
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}
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static inline u32 native_apic_msr_read(u32 reg)
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{
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u32 low, high;
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if (reg == APIC_DFR)
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return -1;
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rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
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return low;
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}
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#ifndef CONFIG_X86_32
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extern int x2apic, x2apic_preenabled;
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extern void check_x2apic(void);
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extern void enable_x2apic(void);
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extern void enable_IR_x2apic(void);
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extern void x2apic_icr_write(u32 low, u32 id);
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static inline int x2apic_enabled(void)
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{
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int msr, msr2;
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if (!cpu_has_x2apic)
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return 0;
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rdmsr(MSR_IA32_APICBASE, msr, msr2);
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if (msr & X2APIC_ENABLE)
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return 1;
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return 0;
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}
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#else
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#define x2apic_enabled() 0
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#endif
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struct apic_ops {
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u32 (*read)(u32 reg);
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void (*write)(u32 reg, u32 v);
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u64 (*icr_read)(void);
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void (*icr_write)(u32 low, u32 high);
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void (*wait_icr_idle)(void);
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u32 (*safe_wait_icr_idle)(void);
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};
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extern struct apic_ops *apic_ops;
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#define apic_read (apic_ops->read)
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#define apic_write (apic_ops->write)
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#define apic_icr_read (apic_ops->icr_read)
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#define apic_icr_write (apic_ops->icr_write)
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#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
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#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
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extern int get_physical_broadcast(void);
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#ifdef CONFIG_X86_64
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static inline void ack_x2APIC_irq(void)
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{
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/* Docs say use 0 for future compatibility */
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native_apic_msr_write(APIC_EOI, 0);
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}
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#endif
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write(APIC_EOI, 0);
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}
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern int verify_local_APIC(void);
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extern void cache_APIC_registers(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void setup_local_APIC(void);
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extern void end_local_APIC_setup(void);
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extern void init_apic_mappings(void);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern int APIC_init_uniprocessor(void);
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extern void enable_NMI_through_LVT0(void);
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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extern void early_init_lapic_mapping(void);
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extern int apic_is_clustered_box(void);
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#else
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static inline int apic_is_clustered_box(void)
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{
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return 0;
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}
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#endif
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extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
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extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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static inline void init_apic_mappings(void) { }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#endif /* ASM_X86__APIC_H */
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