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x86, um: ... and asm-x86 move

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Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Al Viro
2008-08-17 21:05:42 -04:00
committed by H. Peter Anvin
parent 8ede0bdb63
commit bb8985586b
340 changed files with 11 additions and 11 deletions
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94
arch/x86/include/asm/uv/bios.h Normal file
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#ifndef ASM_X86__UV__BIOS_H
#define ASM_X86__UV__BIOS_H
/*
* UV BIOS layer definitions.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
* Copyright (c) Russ Anderson
*/
#include <linux/rtc.h>
/*
* Values for the BIOS calls. It is passed as the first * argument in the
* BIOS call. Passing any other value in the first argument will result
* in a BIOS_STATUS_UNIMPLEMENTED return status.
*/
enum uv_bios_cmd {
UV_BIOS_COMMON,
UV_BIOS_GET_SN_INFO,
UV_BIOS_FREQ_BASE
};
/*
* Status values returned from a BIOS call.
*/
enum {
BIOS_STATUS_SUCCESS = 0,
BIOS_STATUS_UNIMPLEMENTED = -ENOSYS,
BIOS_STATUS_EINVAL = -EINVAL,
BIOS_STATUS_UNAVAIL = -EBUSY
};
/*
* The UV system table describes specific firmware
* capabilities available to the Linux kernel at runtime.
*/
struct uv_systab {
char signature[4]; /* must be "UVST" */
u32 revision; /* distinguish different firmware revs */
u64 function; /* BIOS runtime callback function ptr */
};
enum {
BIOS_FREQ_BASE_PLATFORM = 0,
BIOS_FREQ_BASE_INTERVAL_TIMER = 1,
BIOS_FREQ_BASE_REALTIME_CLOCK = 2
};
union partition_info_u {
u64 val;
struct {
u64 hub_version : 8,
partition_id : 16,
coherence_id : 16,
region_size : 24;
};
};
/*
* bios calls have 6 parameters
*/
extern s64 uv_bios_call(enum uv_bios_cmd, u64, u64, u64, u64, u64);
extern s64 uv_bios_call_irqsave(enum uv_bios_cmd, u64, u64, u64, u64, u64);
extern s64 uv_bios_call_reentrant(enum uv_bios_cmd, u64, u64, u64, u64, u64);
extern s64 uv_bios_get_sn_info(int, int *, long *, long *, long *);
extern s64 uv_bios_freq_base(u64, u64 *);
extern void uv_bios_init(void);
extern int uv_type;
extern long sn_partition_id;
extern long uv_coherency_id;
extern long uv_region_size;
#define partition_coherence_id() (uv_coherency_id)
extern struct kobject *sgi_uv_kobj; /* /sys/firmware/sgi_uv */
#endif /* ASM_X86__UV__BIOS_H */

332
arch/x86/include/asm/uv/uv_bau.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV Broadcast Assist Unit definitions
*
* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef ASM_X86__UV__UV_BAU_H
#define ASM_X86__UV__UV_BAU_H
#include <linux/bitmap.h>
#define BITSPERBYTE 8
/*
* Broadcast Assist Unit messaging structures
*
* Selective Broadcast activations are induced by software action
* specifying a particular 8-descriptor "set" via a 6-bit index written
* to an MMR.
* Thus there are 64 unique 512-byte sets of SB descriptors - one set for
* each 6-bit index value. These descriptor sets are mapped in sequence
* starting with set 0 located at the address specified in the
* BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
* set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
*
* We will use 31 sets, one for sending BAU messages from each of the 32
* cpu's on the node.
*
* TLB shootdown will use the first of the 8 descriptors of each set.
* Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
*/
#define UV_ITEMS_PER_DESCRIPTOR 8
#define UV_CPUS_PER_ACT_STATUS 32
#define UV_ACT_STATUS_MASK 0x3
#define UV_ACT_STATUS_SIZE 2
#define UV_ACTIVATION_DESCRIPTOR_SIZE 32
#define UV_DISTRIBUTION_SIZE 256
#define UV_SW_ACK_NPENDING 8
#define UV_NET_ENDPOINT_INTD 0x38
#define UV_DESC_BASE_PNODE_SHIFT 49
#define UV_PAYLOADQ_PNODE_SHIFT 49
#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
/*
* bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
*/
#define DESC_STATUS_IDLE 0
#define DESC_STATUS_ACTIVE 1
#define DESC_STATUS_DESTINATION_TIMEOUT 2
#define DESC_STATUS_SOURCE_TIMEOUT 3
/*
* source side threshholds at which message retries print a warning
*/
#define SOURCE_TIMEOUT_LIMIT 20
#define DESTINATION_TIMEOUT_LIMIT 20
/*
* number of entries in the destination side payload queue
*/
#define DEST_Q_SIZE 17
/*
* number of destination side software ack resources
*/
#define DEST_NUM_RESOURCES 8
#define MAX_CPUS_PER_NODE 32
/*
* completion statuses for sending a TLB flush message
*/
#define FLUSH_RETRY 1
#define FLUSH_GIVEUP 2
#define FLUSH_COMPLETE 3
/*
* Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
* If the 'multilevel' flag in the header portion of the descriptor
* has been set to 0, then endpoint multi-unicast mode is selected.
* The distribution specification (32 bytes) is interpreted as a 256-bit
* distribution vector. Adjacent bits correspond to consecutive even numbered
* nodeIDs. The result of adding the index of a given bit to the 15-bit
* 'base_dest_nodeid' field of the header corresponds to the
* destination nodeID associated with that specified bit.
*/
struct bau_target_nodemask {
unsigned long bits[BITS_TO_LONGS(256)];
};
/*
* mask of cpu's on a node
* (during initialization we need to check that unsigned long has
* enough bits for max. cpu's per node)
*/
struct bau_local_cpumask {
unsigned long bits;
};
/*
* Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
* only 12 bytes (96 bits) of the payload area are usable.
* An additional 3 bytes (bits 27:4) of the header address are carried
* to the next bytes of the destination payload queue.
* And an additional 2 bytes of the header Suppl_A field are also
* carried to the destination payload queue.
* But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
* of the destination payload queue, which is written by the hardware
* with the s/w ack resource bit vector.
* [ effective message contents (16 bytes (128 bits) maximum), not counting
* the s/w ack bit vector ]
*/
/*
* The payload is software-defined for INTD transactions
*/
struct bau_msg_payload {
unsigned long address; /* signifies a page or all TLB's
of the cpu */
/* 64 bits */
unsigned short sending_cpu; /* filled in by sender */
/* 16 bits */
unsigned short acknowledge_count;/* filled in by destination */
/* 16 bits */
unsigned int reserved1:32; /* not usable */
};
/*
* Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
* see table 4.2.3.0.1 in broacast_assist spec.
*/
struct bau_msg_header {
int dest_subnodeid:6; /* must be zero */
/* bits 5:0 */
int base_dest_nodeid:15; /* nasid>>1 (pnode) of first bit in node_map */
/* bits 20:6 */
int command:8; /* message type */
/* bits 28:21 */
/* 0x38: SN3net EndPoint Message */
int rsvd_1:3; /* must be zero */
/* bits 31:29 */
/* int will align on 32 bits */
int rsvd_2:9; /* must be zero */
/* bits 40:32 */
/* Suppl_A is 56-41 */
int payload_2a:8; /* becomes byte 16 of msg */
/* bits 48:41 */ /* not currently using */
int payload_2b:8; /* becomes byte 17 of msg */
/* bits 56:49 */ /* not currently using */
/* Address field (96:57) is never used as an
address (these are address bits 42:3) */
int rsvd_3:1; /* must be zero */
/* bit 57 */
/* address bits 27:4 are payload */
/* these 24 bits become bytes 12-14 of msg */
int replied_to:1; /* sent as 0 by the source to byte 12 */
/* bit 58 */
int payload_1a:5; /* not currently used */
/* bits 63:59 */
int payload_1b:8; /* not currently used */
/* bits 71:64 */
int payload_1c:8; /* not currently used */
/* bits 79:72 */
int payload_1d:2; /* not currently used */
/* bits 81:80 */
int rsvd_4:7; /* must be zero */
/* bits 88:82 */
int sw_ack_flag:1; /* software acknowledge flag */
/* bit 89 */
/* INTD trasactions at destination are to
wait for software acknowledge */
int rsvd_5:6; /* must be zero */
/* bits 95:90 */
int rsvd_6:5; /* must be zero */
/* bits 100:96 */
int int_both:1; /* if 1, interrupt both sockets on the blade */
/* bit 101*/
int fairness:3; /* usually zero */
/* bits 104:102 */
int multilevel:1; /* multi-level multicast format */
/* bit 105 */
/* 0 for TLB: endpoint multi-unicast messages */
int chaining:1; /* next descriptor is part of this activation*/
/* bit 106 */
int rsvd_7:21; /* must be zero */
/* bits 127:107 */
};
/*
* The activation descriptor:
* The format of the message to send, plus all accompanying control
* Should be 64 bytes
*/
struct bau_desc {
struct bau_target_nodemask distribution;
/*
* message template, consisting of header and payload:
*/
struct bau_msg_header header;
struct bau_msg_payload payload;
};
/*
* -payload-- ---------header------
* bytes 0-11 bits 41-56 bits 58-81
* A B (2) C (3)
*
* A/B/C are moved to:
* A C B
* bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
* ------------payload queue-----------
*/
/*
* The payload queue on the destination side is an array of these.
* With BAU_MISC_CONTROL set for software acknowledge mode, the messages
* are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
* bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
* (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
* sw_ack_vector and payload_2)
* "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
* Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
* operation."
*/
struct bau_payload_queue_entry {
unsigned long address; /* signifies a page or all TLB's
of the cpu */
/* 64 bits, bytes 0-7 */
unsigned short sending_cpu; /* cpu that sent the message */
/* 16 bits, bytes 8-9 */
unsigned short acknowledge_count; /* filled in by destination */
/* 16 bits, bytes 10-11 */
unsigned short replied_to:1; /* sent as 0 by the source */
/* 1 bit */
unsigned short unused1:7; /* not currently using */
/* 7 bits: byte 12) */
unsigned char unused2[2]; /* not currently using */
/* bytes 13-14 */
unsigned char sw_ack_vector; /* filled in by the hardware */
/* byte 15 (bits 127:120) */
unsigned char unused4[3]; /* not currently using bytes 17-19 */
/* bytes 17-19 */
int number_of_cpus; /* filled in at destination */
/* 32 bits, bytes 20-23 (aligned) */
unsigned char unused5[8]; /* not using */
/* bytes 24-31 */
};
/*
* one for every slot in the destination payload queue
*/
struct bau_msg_status {
struct bau_local_cpumask seen_by; /* map of cpu's */
};
/*
* one for every slot in the destination software ack resources
*/
struct bau_sw_ack_status {
struct bau_payload_queue_entry *msg; /* associated message */
int watcher; /* cpu monitoring, or -1 */
};
/*
* one on every node and per-cpu; to locate the software tables
*/
struct bau_control {
struct bau_desc *descriptor_base;
struct bau_payload_queue_entry *bau_msg_head;
struct bau_payload_queue_entry *va_queue_first;
struct bau_payload_queue_entry *va_queue_last;
struct bau_msg_status *msg_statuses;
int *watching; /* pointer to array */
};
/*
* This structure is allocated per_cpu for UV TLB shootdown statistics.
*/
struct ptc_stats {
unsigned long ptc_i; /* number of IPI-style flushes */
unsigned long requestor; /* number of nodes this cpu sent to */
unsigned long requestee; /* times cpu was remotely requested */
unsigned long alltlb; /* times all tlb's on this cpu were flushed */
unsigned long onetlb; /* times just one tlb on this cpu was flushed */
unsigned long s_retry; /* retries on source side timeouts */
unsigned long d_retry; /* retries on destination side timeouts */
unsigned long sflush; /* cycles spent in uv_flush_tlb_others */
unsigned long dflush; /* cycles spent on destination side */
unsigned long retriesok; /* successes on retries */
unsigned long nomsg; /* interrupts with no message */
unsigned long multmsg; /* interrupts with multiple messages */
unsigned long ntargeted;/* nodes targeted */
};
static inline int bau_node_isset(int node, struct bau_target_nodemask *dstp)
{
return constant_test_bit(node, &dstp->bits[0]);
}
static inline void bau_node_set(int node, struct bau_target_nodemask *dstp)
{
__set_bit(node, &dstp->bits[0]);
}
static inline void bau_nodes_clear(struct bau_target_nodemask *dstp, int nbits)
{
bitmap_zero(&dstp->bits[0], nbits);
}
static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
{
bitmap_zero(&dstp->bits, nbits);
}
#define cpubit_isset(cpu, bau_local_cpumask) \
test_bit((cpu), (bau_local_cpumask).bits)
extern int uv_flush_tlb_others(cpumask_t *, struct mm_struct *, unsigned long);
extern void uv_bau_message_intr1(void);
extern void uv_bau_timeout_intr1(void);
#endif /* ASM_X86__UV__UV_BAU_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV architectural definitions
*
* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef ASM_X86__UV__UV_HUB_H
#define ASM_X86__UV__UV_HUB_H
#include <linux/numa.h>
#include <linux/percpu.h>
#include <asm/types.h>
#include <asm/percpu.h>
/*
* Addressing Terminology
*
* M - The low M bits of a physical address represent the offset
* into the blade local memory. RAM memory on a blade is physically
* contiguous (although various IO spaces may punch holes in
* it)..
*
* N - Number of bits in the node portion of a socket physical
* address.
*
* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
* routers always have low bit of 1, C/MBricks have low bit
* equal to 0. Most addressing macros that target UV hub chips
* right shift the NASID by 1 to exclude the always-zero bit.
* NASIDs contain up to 15 bits.
*
* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
* of nasids.
*
* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
* of the nasid for socket usage.
*
*
* NumaLink Global Physical Address Format:
* +--------------------------------+---------------------+
* |00..000| GNODE | NodeOffset |
* +--------------------------------+---------------------+
* |<-------53 - M bits --->|<--------M bits ----->
*
* M - number of node offset bits (35 .. 40)
*
*
* Memory/UV-HUB Processor Socket Address Format:
* +----------------+---------------+---------------------+
* |00..000000000000| PNODE | NodeOffset |
* +----------------+---------------+---------------------+
* <--- N bits --->|<--------M bits ----->
*
* M - number of node offset bits (35 .. 40)
* N - number of PNODE bits (0 .. 10)
*
* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
* The actual values are configuration dependent and are set at
* boot time. M & N values are set by the hardware/BIOS at boot.
*
*
* APICID format
* NOTE!!!!!! This is the current format of the APICID. However, code
* should assume that this will change in the future. Use functions
* in this file for all APICID bit manipulations and conversion.
*
* 1111110000000000
* 5432109876543210
* pppppppppplc0cch
* sssssssssss
*
* p = pnode bits
* l = socket number on board
* c = core
* h = hyperthread
* s = bits that are in the SOCKET_ID CSR
*
* Note: Processor only supports 12 bits in the APICID register. The ACPI
* tables hold all 16 bits. Software needs to be aware of this.
*
* Unless otherwise specified, all references to APICID refer to
* the FULL value contained in ACPI tables, not the subset in the
* processor APICID register.
*/
/*
* Maximum number of bricks in all partitions and in all coherency domains.
* This is the total number of bricks accessible in the numalink fabric. It
* includes all C & M bricks. Routers are NOT included.
*
* This value is also the value of the maximum number of non-router NASIDs
* in the numalink fabric.
*
* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
*/
#define UV_MAX_NUMALINK_BLADES 16384
/*
* Maximum number of C/Mbricks within a software SSI (hardware may support
* more).
*/
#define UV_MAX_SSI_BLADES 256
/*
* The largest possible NASID of a C or M brick (+ 2)
*/
#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
/*
* The following defines attributes of the HUB chip. These attributes are
* frequently referenced and are kept in the per-cpu data areas of each cpu.
* They are kept together in a struct to minimize cache misses.
*/
struct uv_hub_info_s {
unsigned long global_mmr_base;
unsigned long gpa_mask;
unsigned long gnode_upper;
unsigned long lowmem_remap_top;
unsigned long lowmem_remap_base;
unsigned short pnode;
unsigned short pnode_mask;
unsigned short coherency_domain_number;
unsigned short numa_blade_id;
unsigned char blade_processor_id;
unsigned char m_val;
unsigned char n_val;
};
DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
/*
* Local & Global MMR space macros.
* Note: macros are intended to be used ONLY by inline functions
* in this file - not by other kernel code.
* n - NASID (full 15-bit global nasid)
* g - GNODE (full 15-bit global nasid, right shifted 1)
* p - PNODE (local part of nsids, right shifted 1)
*/
#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
#define UV_LOCAL_MMR_BASE 0xf4000000UL
#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
#define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
#define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
#define UV_APIC_PNODE_SHIFT 6
/*
* Macros for converting between kernel virtual addresses, socket local physical
* addresses, and UV global physical addresses.
* Note: use the standard __pa() & __va() macros for converting
* between socket virtual and socket physical addresses.
*/
/* socket phys RAM --> UV global physical address */
static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
{
if (paddr < uv_hub_info->lowmem_remap_top)
paddr += uv_hub_info->lowmem_remap_base;
return paddr | uv_hub_info->gnode_upper;
}
/* socket virtual --> UV global physical address */
static inline unsigned long uv_gpa(void *v)
{
return __pa(v) | uv_hub_info->gnode_upper;
}
/* socket virtual --> UV global physical address */
static inline void *uv_vgpa(void *v)
{
return (void *)uv_gpa(v);
}
/* UV global physical address --> socket virtual */
static inline void *uv_va(unsigned long gpa)
{
return __va(gpa & uv_hub_info->gpa_mask);
}
/* pnode, offset --> socket virtual */
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
{
return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
}
/*
* Extract a PNODE from an APICID (full apicid, not processor subset)
*/
static inline int uv_apicid_to_pnode(int apicid)
{
return (apicid >> UV_APIC_PNODE_SHIFT);
}
/*
* Access global MMRs using the low memory MMR32 space. This region supports
* faster MMR access but not all MMRs are accessible in this space.
*/
static inline unsigned long *uv_global_mmr32_address(int pnode,
unsigned long offset)
{
return __va(UV_GLOBAL_MMR32_BASE |
UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
}
static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
unsigned long val)
{
*uv_global_mmr32_address(pnode, offset) = val;
}
static inline unsigned long uv_read_global_mmr32(int pnode,
unsigned long offset)
{
return *uv_global_mmr32_address(pnode, offset);
}
/*
* Access Global MMR space using the MMR space located at the top of physical
* memory.
*/
static inline unsigned long *uv_global_mmr64_address(int pnode,
unsigned long offset)
{
return __va(UV_GLOBAL_MMR64_BASE |
UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
}
static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
unsigned long val)
{
*uv_global_mmr64_address(pnode, offset) = val;
}
static inline unsigned long uv_read_global_mmr64(int pnode,
unsigned long offset)
{
return *uv_global_mmr64_address(pnode, offset);
}
/*
* Access hub local MMRs. Faster than using global space but only local MMRs
* are accessible.
*/
static inline unsigned long *uv_local_mmr_address(unsigned long offset)
{
return __va(UV_LOCAL_MMR_BASE | offset);
}
static inline unsigned long uv_read_local_mmr(unsigned long offset)
{
return *uv_local_mmr_address(offset);
}
static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
{
*uv_local_mmr_address(offset) = val;
}
/*
* Structures and definitions for converting between cpu, node, pnode, and blade
* numbers.
*/
struct uv_blade_info {
unsigned short nr_possible_cpus;
unsigned short nr_online_cpus;
unsigned short pnode;
};
extern struct uv_blade_info *uv_blade_info;
extern short *uv_node_to_blade;
extern short *uv_cpu_to_blade;
extern short uv_possible_blades;
/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
static inline int uv_blade_processor_id(void)
{
return uv_hub_info->blade_processor_id;
}
/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
static inline int uv_numa_blade_id(void)
{
return uv_hub_info->numa_blade_id;
}
/* Convert a cpu number to the the UV blade number */
static inline int uv_cpu_to_blade_id(int cpu)
{
return uv_cpu_to_blade[cpu];
}
/* Convert linux node number to the UV blade number */
static inline int uv_node_to_blade_id(int nid)
{
return uv_node_to_blade[nid];
}
/* Convert a blade id to the PNODE of the blade */
static inline int uv_blade_to_pnode(int bid)
{
return uv_blade_info[bid].pnode;
}
/* Determine the number of possible cpus on a blade */
static inline int uv_blade_nr_possible_cpus(int bid)
{
return uv_blade_info[bid].nr_possible_cpus;
}
/* Determine the number of online cpus on a blade */
static inline int uv_blade_nr_online_cpus(int bid)
{
return uv_blade_info[bid].nr_online_cpus;
}
/* Convert a cpu id to the PNODE of the blade containing the cpu */
static inline int uv_cpu_to_pnode(int cpu)
{
return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
}
/* Convert a linux node number to the PNODE of the blade */
static inline int uv_node_to_pnode(int nid)
{
return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
}
/* Maximum possible number of blades */
static inline int uv_num_possible_blades(void)
{
return uv_possible_blades;
}
#endif /* ASM_X86__UV__UV_HUB_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV IRQ definitions
*
* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef ASM_X86__UV__UV_IRQ_H
#define ASM_X86__UV__UV_IRQ_H
/* If a generic version of this structure gets defined, eliminate this one. */
struct uv_IO_APIC_route_entry {
__u64 vector : 8,
delivery_mode : 3,
dest_mode : 1,
delivery_status : 1,
polarity : 1,
__reserved_1 : 1,
trigger : 1,
mask : 1,
__reserved_2 : 15,
dest : 32;
};
extern struct irq_chip uv_irq_chip;
extern int arch_enable_uv_irq(char *, unsigned int, int, int, unsigned long);
extern void arch_disable_uv_irq(int, unsigned long);
extern int uv_setup_irq(char *, int, int, unsigned long);
extern void uv_teardown_irq(unsigned int, int, unsigned long);
#endif /* ASM_X86__UV__UV_IRQ_H */

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arch/x86/include/asm/uv/uv_mmrs.h Normal file
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