drm/radeon/kms: prefer high post dividers in legacy pll algo
the hw prefers higher post dividers Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie
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@@ -513,7 +513,7 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
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max_fractional_feed_div = pll->max_frac_feedback_div;
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max_fractional_feed_div = pll->max_frac_feedback_div;
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}
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}
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for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
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for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
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uint32_t ref_div;
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uint32_t ref_div;
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if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
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if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
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