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[ARM] 4882/2: Correction for S3C2410 clkout generation

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This is a correction for 2 small bugs for the Samsung S3C2410 ARM9 SoC
clocks generator

Signed-off-by: Davide Rizzo <davide@elpa.it>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Davide Rizzo
2008-05-03 07:53:14 +01:00
committed by Russell King
parent 649de51b88
commit bdd0f5f06e
1 changed files with 2 additions and 2 deletions
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4
arch/arm/plat-s3c24xx/clock.c
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@@ -411,7 +411,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
clk->parent = parent; clk->parent = parent;
if (clk == &s3c24xx_dclk0) if (clk == &s3c24xx_clkout0)
mask = S3C2410_MISCCR_CLK0_MASK; mask = S3C2410_MISCCR_CLK0_MASK;
else { else {
source <<= 4; source <<= 4;
@@ -437,7 +437,7 @@ struct clk s3c24xx_dclk0 = {
struct clk s3c24xx_dclk1 = { struct clk s3c24xx_dclk1 = {
.name = "dclk1", .name = "dclk1",
.id = -1, .id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN, .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable, .enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent, .set_parent = s3c24xx_dclk_setparent,
.set_rate = s3c24xx_set_dclk_rate, .set_rate = s3c24xx_set_dclk_rate,