[PATCH] sh: IRQ handler updates
This moves the various IRQ controller drivers into a new subdirectory, and also extends the INTC2 IRQ handler to also deal with SH7760 and SH7780 interrupts, rather than just ST-40. The old CONFIG_SH_GENERIC has also been removed from the IRQ definitions, as new ports are expected to be based off of CONFIG_SH_UNKNOWN. Since there are plenty of incompatible machvecs, CONFIG_SH_GENERIC doesn't make sense anymore. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Paul Mundt
committed by
Linus Torvalds
Linus Torvalds
parent
9d44190eae
commit
bf3a00f88c
@@ -2,15 +2,12 @@
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# Makefile for the Linux/SuperH CPU-specifc backends.
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#
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obj-y := irq_ipr.o irq_imask.o init.o bus.o
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obj-y += irq/ init.o bus.o clock.o
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obj-$(CONFIG_CPU_SH2) += sh2/
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obj-$(CONFIG_CPU_SH3) += sh3/
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obj-$(CONFIG_CPU_SH4) += sh4/
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obj-$(CONFIG_SH_RTC) += rtc.o
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obj-$(CONFIG_SH_RTC) += rtc.o
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obj-$(CONFIG_UBC_WAKEUP) += ubc.o
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obj-$(CONFIG_SH_ADC) += adc.o
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USE_STANDARD_AS_RULE := true
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obj-$(CONFIG_SH_ADC) += adc.o
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7
arch/sh/kernel/cpu/irq/Makefile
Normal file
7
arch/sh/kernel/cpu/irq/Makefile
Normal file
@@ -0,0 +1,7 @@
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#
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# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
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#
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obj-y += ipr.o imask.o
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obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
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obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
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@@ -1,16 +1,12 @@
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/* $Id: irq_imask.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $
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*
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* linux/arch/sh/kernel/irq_imask.c
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/*
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* arch/sh/kernel/cpu/irq/imask.c
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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*
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* Simple interrupt handling using IMASK of SR register.
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*
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*/
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/* NOTE: Will not work on level 15 */
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/kernel_stat.h>
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@@ -19,13 +15,11 @@
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <linux/spinlock.h>
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#include <linux/cache.h>
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#include <linux/irq.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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/* Bitmap of IRQ masked */
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static unsigned long imask_mask = 0x7fff;
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@@ -40,7 +34,7 @@ static void end_imask_irq(unsigned int irq);
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#define IMASK_PRIORITY 15
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static unsigned int startup_imask_irq(unsigned int irq)
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{
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{
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/* Nothing to do */
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return 0; /* never anything pending */
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}
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284
arch/sh/kernel/cpu/irq/intc2.c
Normal file
284
arch/sh/kernel/cpu/irq/intc2.c
Normal file
@@ -0,0 +1,284 @@
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/*
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* Interrupt handling for INTC2-based IRQ.
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*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* These are the "new Hitachi style" interrupts, as present on the
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* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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struct intc2_data {
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unsigned char msk_offset;
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unsigned char msk_shift;
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int (*clear_irq) (int);
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};
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static struct intc2_data intc2_data[NR_INTC2_IRQS];
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static void enable_intc2_irq(unsigned int irq);
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static void disable_intc2_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_intc2_irq disable_intc2_irq
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static void mask_and_ack_intc2(unsigned int);
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static void end_intc2_irq(unsigned int irq);
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static unsigned int startup_intc2_irq(unsigned int irq)
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{
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enable_intc2_irq(irq);
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return 0; /* never anything pending */
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}
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static struct hw_interrupt_type intc2_irq_type = {
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.typename = "INTC2-IRQ",
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.startup = startup_intc2_irq,
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.shutdown = shutdown_intc2_irq,
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.enable = enable_intc2_irq,
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.disable = disable_intc2_irq,
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.ack = mask_and_ack_intc2,
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.end = end_intc2_irq
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};
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static void disable_intc2_irq(unsigned int irq)
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{
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int irq_offset = irq - INTC2_FIRST_IRQ;
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int msk_shift, msk_offset;
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/* Sanity check */
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if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
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return;
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msk_shift = intc2_data[irq_offset].msk_shift;
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msk_offset = intc2_data[irq_offset].msk_offset;
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ctrl_outl(1 << msk_shift,
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INTC2_BASE + INTC2_INTMSK_OFFSET + msk_offset);
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}
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static void enable_intc2_irq(unsigned int irq)
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{
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int irq_offset = irq - INTC2_FIRST_IRQ;
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int msk_shift, msk_offset;
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/* Sanity check */
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if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
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return;
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msk_shift = intc2_data[irq_offset].msk_shift;
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msk_offset = intc2_data[irq_offset].msk_offset;
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ctrl_outl(1 << msk_shift,
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INTC2_BASE + INTC2_INTMSKCLR_OFFSET + msk_offset);
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}
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static void mask_and_ack_intc2(unsigned int irq)
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{
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disable_intc2_irq(irq);
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}
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static void end_intc2_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_intc2_irq(irq);
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if (unlikely(intc2_data[irq - INTC2_FIRST_IRQ].clear_irq))
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intc2_data[irq - INTC2_FIRST_IRQ].clear_irq(irq);
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}
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/*
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* Setup an INTC2 style interrupt.
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* NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
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* allowing the use of the numbers straight out of the datasheet.
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* For example:
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* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
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* would be: ^ ^ ^ ^
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* | | | |
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* make_intc2_irq(84, 0, 16, 0, 13);
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*/
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void make_intc2_irq(unsigned int irq,
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unsigned int ipr_offset, unsigned int ipr_shift,
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unsigned int msk_offset, unsigned int msk_shift,
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unsigned int priority)
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{
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int irq_offset = irq - INTC2_FIRST_IRQ;
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unsigned int flags;
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unsigned long ipr;
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if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
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return;
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disable_irq_nosync(irq);
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/* Fill the data we need */
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intc2_data[irq_offset].msk_offset = msk_offset;
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intc2_data[irq_offset].msk_shift = msk_shift;
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intc2_data[irq_offset].clear_irq = NULL;
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/* Set the priority level */
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local_irq_save(flags);
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ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
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ipr &= ~(0xf << ipr_shift);
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ipr |= priority << ipr_shift;
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ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
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local_irq_restore(flags);
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irq_desc[irq].handler = &intc2_irq_type;
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disable_intc2_irq(irq);
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}
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static struct intc2_init {
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unsigned short irq;
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unsigned char ipr_offset, ipr_shift;
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unsigned char msk_offset, msk_shift;
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unsigned char priority;
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} intc2_init_data[] __initdata = {
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#if defined(CONFIG_CPU_SUBTYPE_ST40)
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{64, 0, 0, 0, 0, 13}, /* PCI serr */
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{65, 0, 4, 0, 1, 13}, /* PCI err */
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{66, 0, 4, 0, 2, 13}, /* PCI ad */
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{67, 0, 4, 0, 3, 13}, /* PCI pwd down */
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{72, 0, 8, 0, 5, 13}, /* DMAC INT0 */
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{73, 0, 8, 0, 6, 13}, /* DMAC INT1 */
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{74, 0, 8, 0, 7, 13}, /* DMAC INT2 */
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{75, 0, 8, 0, 8, 13}, /* DMAC INT3 */
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{76, 0, 8, 0, 9, 13}, /* DMAC INT4 */
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{78, 0, 8, 0, 11, 13}, /* DMAC ERR */
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{80, 0, 12, 0, 12, 13}, /* PIO0 */
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{84, 0, 16, 0, 13, 13}, /* PIO1 */
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{88, 0, 20, 0, 14, 13}, /* PIO2 */
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{112, 4, 0, 4, 0, 13}, /* Mailbox */
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#ifdef CONFIG_CPU_SUBTYPE_ST40GX1
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{116, 4, 4, 4, 4, 13}, /* SSC0 */
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{120, 4, 8, 4, 8, 13}, /* IR Blaster */
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{124, 4, 12, 4, 12, 13}, /* USB host */
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{128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */
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{132, 4, 20, 4, 20, 13}, /* UART0 */
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{134, 4, 20, 4, 22, 13}, /* UART2 */
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{136, 4, 24, 4, 24, 13}, /* IO_PIO0 */
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{140, 4, 28, 4, 28, 13}, /* EMPI */
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{144, 8, 0, 8, 0, 13}, /* MAFE */
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{148, 8, 4, 8, 4, 13}, /* PWM */
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{152, 8, 8, 8, 8, 13}, /* SSC1 */
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{156, 8, 12, 8, 12, 13}, /* IO_PIO1 */
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{160, 8, 16, 8, 16, 13}, /* USB target */
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{164, 8, 20, 8, 20, 13}, /* UART1 */
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{168, 8, 24, 8, 24, 13}, /* Teletext */
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{172, 8, 28, 8, 28, 13}, /* VideoSync VTG */
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{173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */
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{174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */
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#endif
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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/*
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* SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
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*/
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/* INTPRIO0 | INTMSK0 */
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{48, 0, 28, 0, 31, 3}, /* IRQ 4 */
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{49, 0, 24, 0, 30, 3}, /* IRQ 3 */
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{50, 0, 20, 0, 29, 3}, /* IRQ 2 */
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{51, 0, 16, 0, 28, 3}, /* IRQ 1 */
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/* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
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/* INTPRIO4 | INTMSK0 */
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{56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
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{57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
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{58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
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{59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
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{60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
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{61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
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{62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
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{63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
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/* INTPRIO8 | INTMSK0 */
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{52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
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{53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
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{54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
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{55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
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{64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
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{65, 8, 24, 0, 16, 3}, /* LCDC */
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/* 66, 67 unused */
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{68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
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{69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
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{70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
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/* 71 unused */
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{72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
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{73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
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{74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
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{75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
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{76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
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{77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
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{78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
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{79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
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/* | INTMSK4 */
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{80, 8, 4, 4, 23, 3}, /* SIM_ERI */
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{81, 8, 4, 4, 22, 3}, /* SIM_RXI */
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{82, 8, 4, 4, 21, 3}, /* SIM_TXI */
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{83, 8, 4, 4, 20, 3}, /* SIM_TEI */
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{84, 8, 0, 4, 19, 3}, /* HSPII */
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/* INTPRIOC | INTMSK4 */
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/* 85-87 unused/reserved */
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{88, 12, 20, 4, 18, 3}, /* MMCI0 */
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{89, 12, 20, 4, 17, 3}, /* MMCI1 */
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{90, 12, 20, 4, 16, 3}, /* MMCI2 */
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{91, 12, 20, 4, 15, 3}, /* MMCI3 */
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{92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
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/* 93-107 reserved/undocumented */
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{108,12, 4, 4, 1, 3}, /* ADC */
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{109,12, 0, 4, 0, 3}, /* CMTI */
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/* 110-111 reserved/unused */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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{ TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
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#ifdef CONFIG_SH_RTC
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{ RTC_IRQ, 4, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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#endif
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{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
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{ PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
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{ PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
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{ PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
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{ PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
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#endif
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};
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void __init init_IRQ_intc2(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(intc2_init_data); i++) {
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struct intc2_init *p = intc2_init_data + i;
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make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
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p-> msk_offset, p->msk_shift, p->priority);
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}
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}
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/* Adds a termination callback to the interrupt */
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void intc2_add_clear_irq(int irq, int (*fn)(int))
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{
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if (unlikely(irq < INTC2_FIRST_IRQ))
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return;
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intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
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}
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@@ -1,6 +1,5 @@
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/* $Id: irq_ipr.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $
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*
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* linux/arch/sh/kernel/irq_ipr.c
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/*
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* arch/sh/kernel/cpu/irq/ipr.c
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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@@ -109,7 +108,8 @@ static void end_ipr_irq(unsigned int irq)
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enable_ipr_irq(irq);
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}
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void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
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void make_ipr_irq(unsigned int irq, unsigned int addr, int pos,
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int priority, int maskpos)
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{
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disable_irq_nosync(irq);
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ipr_data[irq].addr = addr;
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@@ -120,126 +120,47 @@ void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
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disable_ipr_irq(irq);
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}
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
static unsigned char pint_map[256];
|
||||
static unsigned long portcr_mask = 0;
|
||||
|
||||
static void enable_pint_irq(unsigned int irq);
|
||||
static void disable_pint_irq(unsigned int irq);
|
||||
|
||||
/* shutdown is same as "disable" */
|
||||
#define shutdown_pint_irq disable_pint_irq
|
||||
|
||||
static void mask_and_ack_pint(unsigned int);
|
||||
static void end_pint_irq(unsigned int irq);
|
||||
|
||||
static unsigned int startup_pint_irq(unsigned int irq)
|
||||
{
|
||||
enable_pint_irq(irq);
|
||||
return 0; /* never anything pending */
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type pint_irq_type = {
|
||||
.typename = "PINT-IRQ",
|
||||
.startup = startup_pint_irq,
|
||||
.shutdown = shutdown_pint_irq,
|
||||
.enable = enable_pint_irq,
|
||||
.disable = disable_pint_irq,
|
||||
.ack = mask_and_ack_pint,
|
||||
.end = end_pint_irq
|
||||
};
|
||||
|
||||
static void disable_pint_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long val, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
val = ctrl_inw(INTC_INTER);
|
||||
val &= ~(1 << (irq - PINT_IRQ_BASE));
|
||||
ctrl_outw(val, INTC_INTER); /* disable PINTn */
|
||||
portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void enable_pint_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long val, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
val = ctrl_inw(INTC_INTER);
|
||||
val |= 1 << (irq - PINT_IRQ_BASE);
|
||||
ctrl_outw(val, INTC_INTER); /* enable PINTn */
|
||||
portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void mask_and_ack_pint(unsigned int irq)
|
||||
{
|
||||
disable_pint_irq(irq);
|
||||
}
|
||||
|
||||
static void end_pint_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_pint_irq(irq);
|
||||
}
|
||||
|
||||
void make_pint_irq(unsigned int irq)
|
||||
{
|
||||
disable_irq_nosync(irq);
|
||||
irq_desc[irq].handler = &pint_irq_type;
|
||||
disable_pint_irq(irq);
|
||||
}
|
||||
#endif
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
int i;
|
||||
#endif
|
||||
|
||||
make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
|
||||
make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7780
|
||||
make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY, 0);
|
||||
make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY, 0);
|
||||
#if defined(CONFIG_SH_RTC)
|
||||
make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
|
||||
make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY, 0);
|
||||
#endif
|
||||
|
||||
#ifdef SCI_ERI_IRQ
|
||||
make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);
|
||||
make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);
|
||||
make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);
|
||||
#endif
|
||||
|
||||
#ifdef SCIF1_ERI_IRQ
|
||||
make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
|
||||
make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
|
||||
make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
|
||||
make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
|
||||
make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY, 0);
|
||||
make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0);
|
||||
make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0);
|
||||
make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY, 0);
|
||||
#endif
|
||||
|
||||
#ifdef SCIF_ERI_IRQ
|
||||
make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
|
||||
make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
|
||||
make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
|
||||
make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
|
||||
#endif
|
||||
|
||||
#ifdef IRDA_ERI_IRQ
|
||||
make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
|
||||
make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
|
||||
make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
|
||||
make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
@@ -254,86 +175,32 @@ void __init init_IRQ(void)
|
||||
* You should set corresponding bits of PFC to "00"
|
||||
* to enable these interrupts.
|
||||
*/
|
||||
make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
|
||||
make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
|
||||
make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
|
||||
make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
|
||||
make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
|
||||
make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
|
||||
make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
|
||||
enable_ipr_irq(PINT0_IRQ);
|
||||
enable_ipr_irq(PINT8_IRQ);
|
||||
make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY, 0);
|
||||
make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY, 0);
|
||||
make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY, 0);
|
||||
make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY, 0);
|
||||
make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY, 0);
|
||||
make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY, 0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
for(i = 0; i < 16; i++)
|
||||
make_pint_irq(PINT_IRQ_BASE + i);
|
||||
for(i = 0; i < 256; i++)
|
||||
{
|
||||
if(i & 1) pint_map[i] = 0;
|
||||
else if(i & 2) pint_map[i] = 1;
|
||||
else if(i & 4) pint_map[i] = 2;
|
||||
else if(i & 8) pint_map[i] = 3;
|
||||
else if(i & 0x10) pint_map[i] = 4;
|
||||
else if(i & 0x20) pint_map[i] = 5;
|
||||
else if(i & 0x40) pint_map[i] = 6;
|
||||
else if(i & 0x80) pint_map[i] = 7;
|
||||
}
|
||||
#endif /* !CONFIG_CPU_SUBTYPE_SH7300 */
|
||||
#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 || CONFIG_CPU_SUBTYPE_SH7300*/
|
||||
#ifdef CONFIG_CPU_HAS_PINT_IRQ
|
||||
init_IRQ_pint();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_ST40
|
||||
#ifdef CONFIG_CPU_HAS_INTC2_IRQ
|
||||
init_IRQ_intc2();
|
||||
#endif
|
||||
|
||||
/* Perform the machine specific initialisation */
|
||||
if (sh_mv.mv_init_irq != NULL) {
|
||||
if (sh_mv.mv_init_irq != NULL)
|
||||
sh_mv.mv_init_irq();
|
||||
}
|
||||
}
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
|
||||
#if !defined(CONFIG_CPU_HAS_PINT_IRQ)
|
||||
int ipr_irq_demux(int irq)
|
||||
{
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
unsigned long creg, dreg, d, sav;
|
||||
|
||||
if(irq == PINT0_IRQ)
|
||||
{
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
|
||||
creg = PORT_PACR;
|
||||
dreg = PORT_PADR;
|
||||
#else
|
||||
creg = PORT_PCCR;
|
||||
dreg = PORT_PCDR;
|
||||
#endif
|
||||
sav = ctrl_inw(creg);
|
||||
ctrl_outw(sav | portcr_mask, creg);
|
||||
d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff;
|
||||
ctrl_outw(sav, creg);
|
||||
if(d == 0) return irq;
|
||||
return PINT_IRQ_BASE + pint_map[d];
|
||||
}
|
||||
else if(irq == PINT8_IRQ)
|
||||
{
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
|
||||
creg = PORT_PBCR;
|
||||
dreg = PORT_PBDR;
|
||||
#else
|
||||
creg = PORT_PFCR;
|
||||
dreg = PORT_PFDR;
|
||||
#endif
|
||||
sav = ctrl_inw(creg);
|
||||
ctrl_outw(sav | (portcr_mask >> 16), creg);
|
||||
d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff;
|
||||
ctrl_outw(sav, creg);
|
||||
if(d == 0) return irq;
|
||||
return PINT_IRQ_BASE + 8 + pint_map[d];
|
||||
}
|
||||
#endif
|
||||
return irq;
|
||||
}
|
||||
#endif
|
||||
|
||||
EXPORT_SYMBOL(make_ipr_irq);
|
||||
|
||||
169
arch/sh/kernel/cpu/irq/pint.c
Normal file
169
arch/sh/kernel/cpu/irq/pint.c
Normal file
@@ -0,0 +1,169 @@
|
||||
/*
|
||||
* arch/sh/kernel/cpu/irq/pint.c - Interrupt handling for PINT-based IRQs.
|
||||
*
|
||||
* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
|
||||
* Copyright (C) 2000 Kazumoto Kojima
|
||||
* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machvec.h>
|
||||
|
||||
static unsigned char pint_map[256];
|
||||
static unsigned long portcr_mask;
|
||||
|
||||
static void enable_pint_irq(unsigned int irq);
|
||||
static void disable_pint_irq(unsigned int irq);
|
||||
|
||||
/* shutdown is same as "disable" */
|
||||
#define shutdown_pint_irq disable_pint_irq
|
||||
|
||||
static void mask_and_ack_pint(unsigned int);
|
||||
static void end_pint_irq(unsigned int irq);
|
||||
|
||||
static unsigned int startup_pint_irq(unsigned int irq)
|
||||
{
|
||||
enable_pint_irq(irq);
|
||||
return 0; /* never anything pending */
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type pint_irq_type = {
|
||||
.typename = "PINT-IRQ",
|
||||
.startup = startup_pint_irq,
|
||||
.shutdown = shutdown_pint_irq,
|
||||
.enable = enable_pint_irq,
|
||||
.disable = disable_pint_irq,
|
||||
.ack = mask_and_ack_pint,
|
||||
.end = end_pint_irq
|
||||
};
|
||||
|
||||
static void disable_pint_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long val, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
val = ctrl_inw(INTC_INTER);
|
||||
val &= ~(1 << (irq - PINT_IRQ_BASE));
|
||||
ctrl_outw(val, INTC_INTER); /* disable PINTn */
|
||||
portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void enable_pint_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long val, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
val = ctrl_inw(INTC_INTER);
|
||||
val |= 1 << (irq - PINT_IRQ_BASE);
|
||||
ctrl_outw(val, INTC_INTER); /* enable PINTn */
|
||||
portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void mask_and_ack_pint(unsigned int irq)
|
||||
{
|
||||
disable_pint_irq(irq);
|
||||
}
|
||||
|
||||
static void end_pint_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_pint_irq(irq);
|
||||
}
|
||||
|
||||
void make_pint_irq(unsigned int irq)
|
||||
{
|
||||
disable_irq_nosync(irq);
|
||||
irq_desc[irq].handler = &pint_irq_type;
|
||||
disable_pint_irq(irq);
|
||||
}
|
||||
|
||||
void __init init_IRQ_pint(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
|
||||
make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
|
||||
|
||||
enable_irq(PINT0_IRQ);
|
||||
enable_irq(PINT8_IRQ);
|
||||
|
||||
for(i = 0; i < 16; i++)
|
||||
make_pint_irq(PINT_IRQ_BASE + i);
|
||||
|
||||
for(i = 0; i < 256; i++) {
|
||||
if (i & 1)
|
||||
pint_map[i] = 0;
|
||||
else if (i & 2)
|
||||
pint_map[i] = 1;
|
||||
else if (i & 4)
|
||||
pint_map[i] = 2;
|
||||
else if (i & 8)
|
||||
pint_map[i] = 3;
|
||||
else if (i & 0x10)
|
||||
pint_map[i] = 4;
|
||||
else if (i & 0x20)
|
||||
pint_map[i] = 5;
|
||||
else if (i & 0x40)
|
||||
pint_map[i] = 6;
|
||||
else if (i & 0x80)
|
||||
pint_map[i] = 7;
|
||||
}
|
||||
}
|
||||
|
||||
int ipr_irq_demux(int irq)
|
||||
{
|
||||
unsigned long creg, dreg, d, sav;
|
||||
|
||||
if (irq == PINT0_IRQ) {
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
|
||||
creg = PORT_PACR;
|
||||
dreg = PORT_PADR;
|
||||
#else
|
||||
creg = PORT_PCCR;
|
||||
dreg = PORT_PCDR;
|
||||
#endif
|
||||
sav = ctrl_inw(creg);
|
||||
ctrl_outw(sav | portcr_mask, creg);
|
||||
d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) &
|
||||
ctrl_inw(INTC_INTER) & 0xff;
|
||||
ctrl_outw(sav, creg);
|
||||
|
||||
if (d == 0)
|
||||
return irq;
|
||||
|
||||
return PINT_IRQ_BASE + pint_map[d];
|
||||
} else if (irq == PINT8_IRQ) {
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
|
||||
creg = PORT_PBCR;
|
||||
dreg = PORT_PBDR;
|
||||
#else
|
||||
creg = PORT_PFCR;
|
||||
dreg = PORT_PFDR;
|
||||
#endif
|
||||
sav = ctrl_inw(creg);
|
||||
ctrl_outw(sav | (portcr_mask >> 16), creg);
|
||||
d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) &
|
||||
(ctrl_inw(INTC_INTER) >> 8) & 0xff;
|
||||
ctrl_outw(sav, creg);
|
||||
|
||||
if (d == 0)
|
||||
return irq;
|
||||
|
||||
return PINT_IRQ_BASE + 8 + pint_map[d];
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
@@ -1,222 +0,0 @@
|
||||
/*
|
||||
* linux/arch/sh/kernel/irq_intc2.c
|
||||
*
|
||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
||||
*
|
||||
* May be copied or modified under the terms of the GNU General Public
|
||||
* License. See linux/COPYING for more information.
|
||||
*
|
||||
* Interrupt handling for INTC2-based IRQ.
|
||||
*
|
||||
* These are the "new Hitachi style" interrupts, as present on the
|
||||
* Hitachi 7751 and the STM ST40 STB1.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machvec.h>
|
||||
|
||||
|
||||
struct intc2_data {
|
||||
unsigned char msk_offset;
|
||||
unsigned char msk_shift;
|
||||
#ifdef CONFIG_CPU_SUBTYPE_ST40
|
||||
int (*clear_irq) (int);
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
static struct intc2_data intc2_data[NR_INTC2_IRQS];
|
||||
|
||||
static void enable_intc2_irq(unsigned int irq);
|
||||
static void disable_intc2_irq(unsigned int irq);
|
||||
|
||||
/* shutdown is same as "disable" */
|
||||
#define shutdown_intc2_irq disable_intc2_irq
|
||||
|
||||
static void mask_and_ack_intc2(unsigned int);
|
||||
static void end_intc2_irq(unsigned int irq);
|
||||
|
||||
static unsigned int startup_intc2_irq(unsigned int irq)
|
||||
{
|
||||
enable_intc2_irq(irq);
|
||||
return 0; /* never anything pending */
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type intc2_irq_type = {
|
||||
.typename = "INTC2-IRQ",
|
||||
.startup = startup_intc2_irq,
|
||||
.shutdown = shutdown_intc2_irq,
|
||||
.enable = enable_intc2_irq,
|
||||
.disable = disable_intc2_irq,
|
||||
.ack = mask_and_ack_intc2,
|
||||
.end = end_intc2_irq
|
||||
};
|
||||
|
||||
static void disable_intc2_irq(unsigned int irq)
|
||||
{
|
||||
int irq_offset = irq - INTC2_FIRST_IRQ;
|
||||
int msk_shift, msk_offset;
|
||||
|
||||
// Sanity check
|
||||
if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
|
||||
return;
|
||||
|
||||
msk_shift = intc2_data[irq_offset].msk_shift;
|
||||
msk_offset = intc2_data[irq_offset].msk_offset;
|
||||
|
||||
ctrl_outl(1<<msk_shift,
|
||||
INTC2_BASE+INTC2_INTMSK_OFFSET+msk_offset);
|
||||
}
|
||||
|
||||
static void enable_intc2_irq(unsigned int irq)
|
||||
{
|
||||
int irq_offset = irq - INTC2_FIRST_IRQ;
|
||||
int msk_shift, msk_offset;
|
||||
|
||||
/* Sanity check */
|
||||
if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
|
||||
return;
|
||||
|
||||
msk_shift = intc2_data[irq_offset].msk_shift;
|
||||
msk_offset = intc2_data[irq_offset].msk_offset;
|
||||
|
||||
ctrl_outl(1<<msk_shift,
|
||||
INTC2_BASE+INTC2_INTMSKCLR_OFFSET+msk_offset);
|
||||
}
|
||||
|
||||
static void mask_and_ack_intc2(unsigned int irq)
|
||||
{
|
||||
disable_intc2_irq(irq);
|
||||
}
|
||||
|
||||
static void end_intc2_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_intc2_irq(irq);
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_ST40
|
||||
if (intc2_data[irq - INTC2_FIRST_IRQ].clear_irq)
|
||||
intc2_data[irq - INTC2_FIRST_IRQ].clear_irq (irq);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup an INTC2 style interrupt.
|
||||
* NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
|
||||
* allowing the use of the numbers straight out of the datasheet.
|
||||
* For example:
|
||||
* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
|
||||
* would be: ^ ^ ^ ^
|
||||
* | | | |
|
||||
* make_intc2_irq(84, 0, 16, 0, 13);
|
||||
*/
|
||||
void make_intc2_irq(unsigned int irq,
|
||||
unsigned int ipr_offset, unsigned int ipr_shift,
|
||||
unsigned int msk_offset, unsigned int msk_shift,
|
||||
unsigned int priority)
|
||||
{
|
||||
int irq_offset = irq - INTC2_FIRST_IRQ;
|
||||
unsigned int flags;
|
||||
unsigned long ipr;
|
||||
|
||||
if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
|
||||
return;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
/* Fill the data we need */
|
||||
intc2_data[irq_offset].msk_offset = msk_offset;
|
||||
intc2_data[irq_offset].msk_shift = msk_shift;
|
||||
#ifdef CONFIG_CPU_SUBTYPE_ST40
|
||||
intc2_data[irq_offset].clear_irq = NULL;
|
||||
#endif
|
||||
|
||||
/* Set the priority level */
|
||||
local_irq_save(flags);
|
||||
|
||||
ipr=ctrl_inl(INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset);
|
||||
ipr&=~(0xf<<ipr_shift);
|
||||
ipr|=(priority)<<ipr_shift;
|
||||
ctrl_outl(ipr, INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
irq_desc[irq].handler=&intc2_irq_type;
|
||||
|
||||
disable_intc2_irq(irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_ST40
|
||||
|
||||
struct intc2_init {
|
||||
unsigned short irq;
|
||||
unsigned char ipr_offset, ipr_shift;
|
||||
unsigned char msk_offset, msk_shift;
|
||||
};
|
||||
|
||||
static struct intc2_init intc2_init_data[] __initdata = {
|
||||
{64, 0, 0, 0, 0}, /* PCI serr */
|
||||
{65, 0, 4, 0, 1}, /* PCI err */
|
||||
{66, 0, 4, 0, 2}, /* PCI ad */
|
||||
{67, 0, 4, 0, 3}, /* PCI pwd down */
|
||||
{72, 0, 8, 0, 5}, /* DMAC INT0 */
|
||||
{73, 0, 8, 0, 6}, /* DMAC INT1 */
|
||||
{74, 0, 8, 0, 7}, /* DMAC INT2 */
|
||||
{75, 0, 8, 0, 8}, /* DMAC INT3 */
|
||||
{76, 0, 8, 0, 9}, /* DMAC INT4 */
|
||||
{78, 0, 8, 0, 11}, /* DMAC ERR */
|
||||
{80, 0, 12, 0, 12}, /* PIO0 */
|
||||
{84, 0, 16, 0, 13}, /* PIO1 */
|
||||
{88, 0, 20, 0, 14}, /* PIO2 */
|
||||
{112, 4, 0, 4, 0}, /* Mailbox */
|
||||
#ifdef CONFIG_CPU_SUBTYPE_ST40GX1
|
||||
{116, 4, 4, 4, 4}, /* SSC0 */
|
||||
{120, 4, 8, 4, 8}, /* IR Blaster */
|
||||
{124, 4, 12, 4, 12}, /* USB host */
|
||||
{128, 4, 16, 4, 16}, /* Video processor BLITTER */
|
||||
{132, 4, 20, 4, 20}, /* UART0 */
|
||||
{134, 4, 20, 4, 22}, /* UART2 */
|
||||
{136, 4, 24, 4, 24}, /* IO_PIO0 */
|
||||
{140, 4, 28, 4, 28}, /* EMPI */
|
||||
{144, 8, 0, 8, 0}, /* MAFE */
|
||||
{148, 8, 4, 8, 4}, /* PWM */
|
||||
{152, 8, 8, 8, 8}, /* SSC1 */
|
||||
{156, 8, 12, 8, 12}, /* IO_PIO1 */
|
||||
{160, 8, 16, 8, 16}, /* USB target */
|
||||
{164, 8, 20, 8, 20}, /* UART1 */
|
||||
{168, 8, 24, 8, 24}, /* Teletext */
|
||||
{172, 8, 28, 8, 28}, /* VideoSync VTG */
|
||||
{173, 8, 28, 8, 29}, /* VideoSync DVP0 */
|
||||
{174, 8, 28, 8, 30}, /* VideoSync DVP1 */
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init init_IRQ_intc2(void)
|
||||
{
|
||||
struct intc2_init *p;
|
||||
|
||||
printk(KERN_ALERT "init_IRQ_intc2\n");
|
||||
|
||||
for (p = intc2_init_data;
|
||||
p<intc2_init_data+ARRAY_SIZE(intc2_init_data);
|
||||
p++) {
|
||||
make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
|
||||
p-> msk_offset, p->msk_shift, 13);
|
||||
}
|
||||
}
|
||||
|
||||
/* Adds a termination callback to the interrupt */
|
||||
void intc2_add_clear_irq(int irq, int (*fn)(int))
|
||||
{
|
||||
if (irq < INTC2_FIRST_IRQ)
|
||||
return;
|
||||
|
||||
intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CPU_SUBTYPE_ST40 */
|
||||
@@ -8,38 +8,13 @@
|
||||
* SuperH version: Copyright (C) 1999 Niibe Yutaka
|
||||
*/
|
||||
|
||||
/*
|
||||
* IRQs are in fact implemented a bit like signal handlers for the kernel.
|
||||
* Naturally it's not a 1:1 relation, but there are similarities.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/smp_lock.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/kallsyms.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/delay.h>
|
||||
#include <asm/irq.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cpu/mmu_context.h>
|
||||
|
||||
/*
|
||||
* 'what should we do if we get a hw irq event on an illegal vector'.
|
||||
@@ -66,7 +41,7 @@ int show_interrupts(struct seq_file *p, void *v)
|
||||
seq_putc(p, '\n');
|
||||
}
|
||||
|
||||
if (i < ACTUAL_NR_IRQS) {
|
||||
if (i < NR_IRQS) {
|
||||
spin_lock_irqsave(&irq_desc[i].lock, flags);
|
||||
action = irq_desc[i].action;
|
||||
if (!action)
|
||||
@@ -86,19 +61,32 @@ unlock:
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7,
|
||||
struct pt_regs regs)
|
||||
{
|
||||
int irq;
|
||||
{
|
||||
int irq = r4;
|
||||
|
||||
irq_enter();
|
||||
asm volatile("stc r2_bank, %0\n\t"
|
||||
"shlr2 %0\n\t"
|
||||
"shlr2 %0\n\t"
|
||||
"shlr %0\n\t"
|
||||
"add #-16, %0\n\t"
|
||||
:"=z" (irq));
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_INTEVT
|
||||
__asm__ __volatile__ (
|
||||
#ifdef CONFIG_CPU_HAS_SR_RB
|
||||
"stc r2_bank, %0\n\t"
|
||||
#else
|
||||
"mov.l @%1, %0\n\t"
|
||||
#endif
|
||||
"shlr2 %0\n\t"
|
||||
"shlr2 %0\n\t"
|
||||
"shlr %0\n\t"
|
||||
"add #-16, %0\n\t"
|
||||
: "=z" (irq), "=r" (r4)
|
||||
: "1" (INTEVT)
|
||||
: "memory"
|
||||
);
|
||||
#endif
|
||||
|
||||
irq = irq_demux(irq);
|
||||
__do_IRQ(irq, ®s);
|
||||
irq_exit();
|
||||
|
||||
Reference in New Issue
Block a user