[PATCH] sh: IRQ handler updates
This moves the various IRQ controller drivers into a new subdirectory, and also extends the INTC2 IRQ handler to also deal with SH7760 and SH7780 interrupts, rather than just ST-40. The old CONFIG_SH_GENERIC has also been removed from the IRQ definitions, as new ports are expected to be based off of CONFIG_SH_UNKNOWN. Since there are plenty of incompatible machvecs, CONFIG_SH_GENERIC doesn't make sense anymore. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Paul Mundt
committed by
Linus Torvalds
Linus Torvalds
parent
9d44190eae
commit
bf3a00f88c
@@ -15,13 +15,20 @@
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#include <asm/machvec.h>
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#include <asm/ptrace.h> /* for pt_regs */
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#if defined(CONFIG_SH_HP600) || \
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#if defined(CONFIG_SH_HP6XX) || \
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defined(CONFIG_SH_RTS7751R2D) || \
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defined(CONFIG_SH_HS7751RVOIP) || \
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defined(CONFIG_SH_SH03)
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defined(CONFIG_SH_HS7751RVOIP) || \
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defined(CONFIG_SH_SH03) || \
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defined(CONFIG_SH_R7780RP) || \
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defined(CONFIG_SH_LANDISK)
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#include <asm/mach/ide.h>
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#endif
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#ifndef CONFIG_CPU_SUBTYPE_SH7780
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#define INTC_DMAC0_MSK 0
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#if defined(CONFIG_CPU_SH3)
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#define INTC_IPRA 0xfffffee2UL
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#define INTC_IPRB 0xfffffee4UL
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@@ -235,8 +242,9 @@
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#define SCIF1_IPR_ADDR INTC_IPRB
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#define SCIF1_IPR_POS 1
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#define SCIF1_PRIORITY 3
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#endif
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#endif
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#endif /* ST40STB1 */
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#endif /* 775x / SH4-202 / ST40STB1 */
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/* NR_IRQS is made from three components:
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* 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
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@@ -245,37 +253,35 @@
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*/
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/* 1. ONCHIP_NR_IRQS */
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#ifdef CONFIG_SH_GENERIC
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#if defined(CONFIG_CPU_SUBTYPE_SH7604)
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# define ONCHIP_NR_IRQS 24 // Actually 21
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#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
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# define ONCHIP_NR_IRQS 64
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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# define ONCHIP_NR_IRQS 32
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#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define ONCHIP_NR_IRQS 64 // Actually 61
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
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# define ONCHIP_NR_IRQS 48 // Actually 44
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#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define ONCHIP_NR_IRQS 112 /* XXX */
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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# define ONCHIP_NR_IRQS 144
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#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
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# define ONCHIP_NR_IRQS 109
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#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
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# define ONCHIP_NR_IRQS 144
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#else
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# if defined(CONFIG_CPU_SUBTYPE_SH7604)
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# define ONCHIP_NR_IRQS 24 // Actually 21
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# elif defined(CONFIG_CPU_SUBTYPE_SH7707)
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# define ONCHIP_NR_IRQS 64
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# define PINT_NR_IRQS 16
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# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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# define ONCHIP_NR_IRQS 32
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# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define ONCHIP_NR_IRQS 64 // Actually 61
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# define PINT_NR_IRQS 16
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# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
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# define ONCHIP_NR_IRQS 48 // Actually 44
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# elif defined(CONFIG_CPU_SUBTYPE_SH7751)
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# define ONCHIP_NR_IRQS 72
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# elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define ONCHIP_NR_IRQS 110
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# elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define ONCHIP_NR_IRQS 72
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# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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# define ONCHIP_NR_IRQS 144
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# elif defined(CONFIG_CPU_SUBTYPE_SH7300)
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# define ONCHIP_NR_IRQS 109
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# endif
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#endif
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/* 2. PINT_NR_IRQS */
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#ifdef CONFIG_SH_GENERIC
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#ifdef CONFIG_SH_UNKNOWN
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# define PINT_NR_IRQS 16
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#else
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# ifndef PINT_NR_IRQS
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@@ -288,22 +294,22 @@
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#endif
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/* 3. OFFCHIP_NR_IRQS */
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#ifdef CONFIG_SH_GENERIC
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#if defined(CONFIG_HD64461)
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# define OFFCHIP_NR_IRQS 18
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#elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
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# define OFFCHIP_NR_IRQS 48
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#elif defined(CONFIG_HD64465)
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# define OFFCHIP_NR_IRQS 16
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#elif defined (CONFIG_SH_EC3104)
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# define OFFCHIP_NR_IRQS 16
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#elif defined (CONFIG_SH_DREAMCAST)
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# define OFFCHIP_NR_IRQS 96
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#elif defined (CONFIG_SH_TITAN)
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# define OFFCHIP_NR_IRQS 4
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#elif defined(CONFIG_SH_UNKNOWN)
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# define OFFCHIP_NR_IRQS 16 /* Must also be last */
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#else
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# if defined(CONFIG_HD64461)
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# define OFFCHIP_NR_IRQS 18
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# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
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# define OFFCHIP_NR_IRQS 48
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# elif defined(CONFIG_HD64465)
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# define OFFCHIP_NR_IRQS 16
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# elif defined (CONFIG_SH_EC3104)
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# define OFFCHIP_NR_IRQS 16
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# elif defined (CONFIG_SH_DREAMCAST)
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# define OFFCHIP_NR_IRQS 96
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# else
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# define OFFCHIP_NR_IRQS 0
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# endif
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# define OFFCHIP_NR_IRQS 0
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#endif
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#if OFFCHIP_NR_IRQS > 0
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@@ -313,16 +319,6 @@
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/* NR_IRQS. 1+2+3 */
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#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
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/* In a generic kernel, NR_IRQS is an upper bound, and we should use
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* ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
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*/
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#ifdef CONFIG_SH_GENERIC
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# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
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#else
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# define ACTUAL_NR_IRQS NR_IRQS
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#endif
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extern void disable_irq(unsigned int);
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extern void disable_irq_nosync(unsigned int);
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extern void enable_irq(unsigned int);
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@@ -542,9 +538,6 @@ extern int ipr_irq_demux(int irq);
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extern int ipr_irq_demux(int irq);
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#define __irq_demux(irq) ipr_irq_demux(irq)
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#else
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#define __irq_demux(irq) irq
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#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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@@ -557,18 +550,35 @@ extern int ipr_irq_demux(int irq);
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#define INTC_ICR_IRLM (1<<7)
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#endif
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#ifdef CONFIG_CPU_SUBTYPE_ST40STB1
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#define INTC2_FIRST_IRQ 64
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#define NR_INTC2_IRQS 25
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#else
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#include <asm/irq-sh7780.h>
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#endif
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/* SH with INTC2-style interrupts */
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#ifdef CONFIG_CPU_HAS_INTC2_IRQ
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#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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#define INTC2_BASE 0xfe080000
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#define INTC2_INTC2MODE (INTC2_BASE+0x80)
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#define INTC2_INTPRI_OFFSET 0x00
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#define INTC2_FIRST_IRQ 64
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#define INTC2_INTREQ_OFFSET 0x20
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#define INTC2_INTMSK_OFFSET 0x40
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#define INTC2_INTMSKCLR_OFFSET 0x60
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#define NR_INTC2_IRQS 25
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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#define INTC2_BASE 0xfe080000
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#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
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#define INTC2_INTREQ_OFFSET 0x20
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#define INTC2_INTMSK_OFFSET 0x40
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#define INTC2_INTMSKCLR_OFFSET 0x60
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#define NR_INTC2_IRQS 64
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define INTC2_BASE 0xffd40000
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#define INTC2_FIRST_IRQ 22
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#define INTC2_INTMSK_OFFSET (0x38)
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#define INTC2_INTMSKCLR_OFFSET (0x3c)
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#define NR_INTC2_IRQS 60
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#endif
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#define INTC2_INTPRI_OFFSET 0x00
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void make_intc2_irq(unsigned int irq,
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unsigned int ipr_offset, unsigned int ipr_shift,
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@@ -577,13 +587,16 @@ void make_intc2_irq(unsigned int irq,
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void init_IRQ_intc2(void);
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void intc2_add_clear_irq(int irq, int (*fn)(int));
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#endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */
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#endif
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static inline int generic_irq_demux(int irq)
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{
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return irq;
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}
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#ifndef __irq_demux
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#define __irq_demux(irq) (irq)
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#endif
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#define irq_canonicalize(irq) (irq)
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#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
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